Ⅰ. Simulation of Si and SiC devices on a Hybrid EV design

Firstly, we will explore a system simulation for a Hybrid EV traction inverter with Si and SiC devices with the final output.

This simulation used a vehicle power module with a package rating of tj(max) = 175 ◦C junction temperature and a typical combustion engine cooling fluid temperature of tf = 105 ◦C. The electrical machine determines the loss-influencing factors such as current, voltage, and power factor. Efficiency optimized speed–torque lookup tables are used as a fast method to define the operating conditions of the inverter. A minimal phase current operated machine for each dc-link voltage is considered without changing its electromagnetic design. The fluid-cooled pin-fin base plate has been proposed as a suitable power module cooling option for Hybrid and electric vehicles. Its thermal transition resistance of 19 mm2 KW has been used for the additional modeling.

The state-space representation of the Thermal Domain Transient Model with the Nonlinear Electrical Domain Loss Model as feedback was simulated with MATLAB/Simulink software.

A Vehicle Physics Model with gearshift was added to generate mission profiles for the HEV traction inverters from standardized drive cycles. The vehicle chosen for the simulations was a 2500-kg HEV–SUV with a gearbox-integrated permanent-magnet synchronous machine(PMSM) (32 poles, 500 Nm, 60 kW). Operating conditions for the simulation are:

1. Constant battery voltage:

a. 350 V for 650-V IGBTs

b. 700 V for 1200-V IGBTs

c. 700 V for 1200-V D-mode-SiC-JFETs

2. 10-kHz switching frequency

A brief overview of the simulation model structure is displayed below.

Figure.1 Simulation model for testing Si and SiC semiconductor traction inverters

The efficiency of the inverters and the electrical machine driving the new European drive cycle (NEDC) showed reduced losses of the SiC inverter, especially at partial load.

Figure.2 Inverter output to Efficiency graph for different power electronics technologies

The time domain simulation and transient modeling are done to test the power semiconductor's reliability and lifetime, considering the load profile and possible redesign of the chip area of the system. The application of the Rainflow-algorithm on the thermal chip time domain responses is a state-of-the-art procedure to count the thermal cycles of the package during the operation for an estimation of the lifetime.

This calculation showed no significant difference between the chip area optimized Si and SiC inverters. The simulation model also yields power losses from which the energy consumption for the semiconductor devices was calculated. The power losses for Si and SiC devices are:

Figure.3 Simulation output for various power electronics devices

Through this experiment of NEDC simulated driving, a possible reduction in energy loss of up to 70% for traction inverters with a 66% reduction in chip area using silicon carbide devices can be achieved as compared to silicon devices.

Ⅱ. Comparative Analysis between Si and SiC devices

Apart from the NEDC simulation, we also aim to study the characteristics and comparative analysis of different Si and SiC semiconductor devices:

1. Device Characterization

The laboratory setup for the investigation of switching behavior was set up with an external temperature controller. The gate driver has been designed to provide a configurable voltage between ±25 V with a maximum peak current of 1 A. The range of switching curves achieved for SiC-D-J-1200, SiC-E-J-1200, and SiC-EMOS-1200 devices is:

Figure.4 Half-bridge switching for SiC-D-J-1200 vs time for voltage, current and junction temperature

Figure.5 Half-bridge switching for SiC-E-J-1200 vs time for voltage, current and junction temperature

Figure.6 Half-bridge switching for SiC-E-MOS-1200 vs time for voltage, current and junction temperature

The turn-off behavior of all half-bridges is comparably fast, and there is no significant difference in the slopes.

A reverse recovery spike of the SiC-D-J-1200 at high currents and temperatures becomes significant during the turn-on of the SiC-body-diode. As a result, the device introduces a moderate ringing into the commutation loop due to steep current slopes, which reach the speed of the turn-off slope. The SiC-E-J1200 shows nearly no reverse recovery behavior due to the SiC JBS-diode. A flat voltage slope characterizes it during turn-on. This leads to significant switching losses. The SiC-E-MOS-1200 half bridge shows the fastest turn-on accompanied by the highest reverse recovery spike, leading to significant ringing in the commutation loop.

2. Thermal characteristics

The below figure shows the thermal characteristics of the device's differential area normalized on-state resistance. The D-mode SiC-JFET, SiC-MOSFET, and Si IGBTs show a flat thermal characteristic. At the same time, the E-mode SiC-JFET reveals a sharp increase in the resistance above 150 ◦ C. The bipolar Si diodes nearly reach an order of magnitude lower differential on-state resistance compared with the unipolar SiC-JBS-Diode, which is in the range of the SiC-FETs.

The voltage offset of the SiC-JBS-Diode decreases with temperature, as is with all the voltage offsets of the silicon devices. Therefore, the value of the SiC-JBS-Diode voltage offset is in the range below the 1200-V and above the 650-V silicon devices for the pictured temperature region.

Figure.7 Resistance vs temperature and voltage vs temperature for different devices

The gate drive current varies in proportion to the chip area and parasitic inductance of the commutation loop varies inversely. Hence, comparing Si and SiC half bridges with the same chip area demonstrated five to ten times higher switching losses for the Si half bridges.

3. Heat Loss vs semiconductor chip areas

Figure.8 Power loss for different chip areas for different devices

The above figure shows the generated and dissipated heat at a set critical operating condition for different chip areas with 400-V dc-link voltage, 173-A peak phase current, 175 ◦C maximum junction temperature, and 10-kHz switching frequency. The results of the above experiment conclude that the minimum permissible chip area of the semiconductor device is given by the intersection of the generated and dissipated power over the chip area curve.

This minimum chip area was calculated numerically. In addition, the resulting minimum cumulated chip area of the traction inverter for a 60-kW electrical drivetrain component of an HEV has been calculated for different switching frequencies and battery voltages.

Figure.9 Chip area vs dc-link voltage at different switching frequencies and battery voltages

The Si inverters show an increase in minimum chip area for higher switching frequencies to dissipate the extra switching loss. In contrast, for SiC inverters, only a slight increase in chip area is needed. As far as comparison between same technology devices are concerned, Si-E-I-0650 technology performs better compared with Si-E-I-1200 for switching frequencies higher than 5 kHz. Also, the SiC-D-J-1200 and SiC-E-MOS-1200 show similar performance and surpass SiC-E-J-1200 due to utilization of the body diode.

Ⅲ. Conclusion

The simulated driving of the NEDC experiment presented in the research paper shows a 70% energy loss and 66% chip area reduction for traction inverters with SiC devices over Si power semiconductors. Through this article, we also presented the loss characterization of SiC semiconductors and dependence on dc-link voltage, current and junction temperature based on the same research paper.