The MOS tube, or metal (Metal)-oxide (Oxide)-semiconductor (Semiconductor) field effect transistor, is a semiconductor device that uses the field effect principle to function.

MOS tubes feature a high input impedance, low noise, great dynamic range, low power consumption, and easy integration when compared to regular bipolar transistors. Switching power supply, ballasts, high-frequency induction heating, and high-frequency inverter welding are all examples of where they're used. In the realm of high-frequency power supply, such as computer and communication power supply, it is becoming increasingly popular.

Types and structures of MOS tubes

MOS tube is a type of  FET  (the other is  JFET  junction field effect transistor). There are two main types of structures: N-channel type and P-channel type; and it is divided into depletion type (when the gate voltage is zero, the drain current is larger) and enhancement type (when the gate voltage is zero, the drain current is smaller) (when the gate voltage is zero, the drain current is also zero, and the drain current must be added after a certain gate voltage). P-channel enhancement  , P-channel depletion, N-channel enhancement  , and N-channel depletion are the four types of MOS tubes that can be manufactured.

Figure. 1 4 Types of MOS Tubes

Each MOS tube has three electrodes: a Gate gate (represented by the letter "G"), a Source source (represented by the letter "S"), and a Drain drain (represented by the letter "D") (represented as "D"). When wiring, the N-power channel's input is D, and the output is S; the P-power channel's input is S, and the output is D; and the enhancement and depletion connection methods are essentially the same.

Figure. 2 Internal Structure of MOS Tube

The source and drain of the N-channel  FET are connected to the N-type semiconductor, while the source and drain of the P-channel FET are connected to the P-type semiconductor, as shown in the structure diagram. The input voltage (or field voltage) controls the output current of the field effect tube, and the input current is either extremely little or none at all, resulting in a high input impedance, which is also why the MOS tube is termed a field effect tube. reason.

Ⅰ. MOSFET working principle

1. The principle of N-channel enhancement  mode field effect transistor

The N-channel enhancement  mode MOS transistor forms a layer of  SiO2  thin film insulating layer on the P-type semiconductor, then photolithographically diffuses two highly doped N-type regions and leads the electrodes (drain D, source S) from the N-type region; a layer of metal aluminum is plated on the  SiO2 insulating layer between the source and drain as the gate G; the P-type semiconductor is called the substrate and is represented by the symbol B.  NMOS  is also known as an insulated gate field effect transistor since the gate and other electrodes are insulated from each other.

Because there is a P-type substrate between the two N+-type areas of the drain and the source, it is equivalent to two back-to-back PN junctions when no voltage is placed between the gate G and the source S, that is, VGS=0. Because the resistance between them is as high as 1012, there is no conductive channel between D and S, the drain current ID will not be generated regardless of the polarity voltage placed between the drain and the source.

Figure. 3 Schematic Diagram of the Structure of N-channel Enhancement Mode MOS Transistor

When the substrate B and the source S are short-circuited and a positive voltage, VGS>0, is applied between the gate G and the source S, as shown in Figure 3(a), between the gate and the substrate is formed. An electric field is created that is directed from the gate to the substrate. The holes near the surface of the P substrate  are repelled and pushed downward by the electric field, while the electrons are attracted by the electric field and move toward the substrate's surface, where they recombine with the holes on the surface to form a depletion layer.

If the VGS voltage is increased further, until it reaches a certain voltage VT, all the holes in the P substrate  's surface layer are repelled and depleted, while a large number of free electrons are attracted to the surface layer, changing its quality from quantity to quality. The "inversion layer," which is an N-type layer in which the free electrons are multi-subs, is generated, as shown in Figure 3. (b).

To generate an N-type conductive channel between the drain and the source, the inversion layer joins the two N+-type areas of the drain D and the source S. The threshold voltage or turn-on voltage, denoted by VGS, is the value of VGS required to begin constructing a conductive channel (th). Obviously, a channel exists only when VGS>VGS(th), and the greater the VGS, the thicker the channel, the lower the channel's on-resistance, and the higher the conductivity; the term "enhanced" is derived from this.

Figure. 4 Schematic Diagram of the Structure Generated by the Depletion Layer and the Inversion Layer

If a positive voltage VDS is placed between the drain electrode D and the source electrode S under the condition VGS>VGS(th), current will flow in the conductive channel. The drain current is a current that flows from the drain to the source. Because the channel has a specific resistance, a voltage drop occurs along the channel, causing the potential of each channel point to gradually fall from the drain to the source area, and it is close to the drain region. The voltage VGD is the smallest, with a value of VGD=VGS-VDS, and the accompanying channel is the thinnest; the voltage VGS is the greatest, with a value of VGS, and the corresponding channel is the thickest.

As a result, the channel's thickness is no longer uniform, and the entire channel is slanted. The channel towards one end of the drain region becomes thinner and thinner as VDS increases.

The channel at the drain end evaporates when VDS reaches a threshold value, such that VGDVGS(th), leaving just the depletion layer, which is referred to as "pre-pinch-off" of the channel, as shown in Figure 4 (a).As VDS rises [that is, VDS>VGS-VGS(th)], the pinch-off point travels closer to the source, as seen in Figure 4. (b).

The voltage drop in the channel region (source S to the pinch-off point) remains constant and equal to VGS-VGS despite the pinch-off point shifting (th). As a result, the excess voltage of VDS [VDS-(VGS-VGS(th)] all falls to the pinch-off region, forming a strong electric field there. Electrons flow from the source to the pinch-off region along the channel during this moment. Due to the strong electric field in the pinch-off zone, electrons will swiftly drift to the drain when they approach the edge of the pinch-off region.

Figure. 5 Schematic Diagram of the Formation of Pre-pinch-off and Pinch-off Area

2. The principle of P-channel enhancement  mode field effect transistor

The enhancement mode for the P-channel The P-type inversion layer is created in the N-type substrate, hence the name MOS tube. Photolithography, diffusion, or other methods are used to create it on an N-type substrate (substrate). The doped P area is taken out of the electrodes (source S and drain D), and a metal gate G is formed between the drain and the source on the SiO2 insulating layer. Its structure and operating principle are similar to that of N-channel MOS transistors, with the exception that the gate-source and drain-source voltage polarities are reversed.

The P-channel enhancement  mode MOS transistor's substrate must be linked to the source during normal operation, and the voltage VDS of the drain to the source must be negative to guarantee that the PN junction between the two P regions and the substrate is maintained. The gate-to-source voltage should also be negative for reverse bias and to generate a conductive channel near the top surface of the substrate.

Figure. 6 Schematic Diagram of the Structure of the P-channel Enhancement Mode MOS Transistor

Figure 6: When VDS=0, the structure of the P-channel enhancement  mode MOS transistor is shown schematically. Because of the insulating layer, there is no current when a negative voltage ratio is placed between the gate and the source, yet the metal gate is provided with electricity to collect negative charges.The positively charged ions form the depletion layer.

The depletion layer spreads as the negative voltage between G and S grows. When the VDS reaches a specific value, the negative charges in the gate attract the holes (minority carriers) in the substrate to the surface, and in the depletion layer, a P-type thin layer termed the inversion layer forms between the insulating layer and the insulating layer, as shown in Figure 6. (2).

The conductive channel between the drain and the source is formed by this inversion layer. The VGS at this point is known as the turn-on voltage VGS(th), and it rises after reaching VGS(th). The more holes generated on the substrate's surface, the thicker the inversion layer becomes. We can regulate the width of the conduction channel with the size of VGS because the width of the depletion layer does not change.

Figure. 7 Schematic Diagram of the Formation of the Depletion Layer and the Inversion Layer of the P-channel Enhancement Mode MOS Transistor

When VDS0 is turned on. When a negative voltage is supplied between D and S after the conductive channel is established, a drain current ID flows between the source and the drain, and ID grows with VDS, causing the channel to flow due to the voltage drop generated by ID along the channel. As illustrated in Figure 7, the voltage between each point on the channel and the gate is no longer equal, and this voltage decreases the influence of the negative electric field in the gate, narrowing the channel from drain to source (1).

The channel appears pre-pinch-off at the drain when VDS is increased to make VGD=VGS (that is, VDS=VGS-VGS(TH)) (2). As VDS is increased, the pinch-off area is only slightly prolonged, and the channel current essentially retains the pre-pinch-off value. The resulting drain current ID is roughly independent of VDS at the pinch-off area near the drain.

Figure. 8 Schematic Diagram of P-channel Enhancement Mode MOS Transistor Pre-pinch-off and Pinch-off Region Formation

3. The principle of N-channel depletion FET

The N-channel depletion-mode MOS transistor has a structure similar to the enhancement-mode MOS transistor. The only difference is that when the gate voltage VGS=0, the channel of the N-channel depletion-mode MOS transistor already exists. This is due to ion implantation during the manufacturing process, which pre-dopes the N-channel with a substantial amount of metal positive ions on the surface of the substrate between D and S and the SiO2 insulating layer under the gate. The channel is sometimes known as the first channel.

When VGS=0, these positive ions have induced an inversion layer and formed a channel, therefore there is a drain current as long as the drain-source voltage is present; when VGS>0, the ID will increase further; VGS0 The drain current gradually reduces as VGS drops until ID=0. The pinch-off voltage, also known as the threshold voltage, is represented by the symbol VGS(off) or Up, and corresponds to ID=0.

Because the channel between the drain and the source exists while the depletion MOSFET  is VGS=0, there is ID flow as long as VDS is provided. When the forward gate voltage VGS is increased, the electric field between the gate and the substrate induces more electrons in the channel, which thickens the channel and increases its conductance.

When a negative voltage is applied to the gate (i.e. VGS 0), positive charges are induced on the corresponding substrate surface, and these positive charges cancel the electrons in the N-channel, resulting in the formation of a depletion layer on the substrate surface. The depletion area extends to the entire channel when the negative gate voltage reaches a particular voltage VGS (off), and the channel is entirely pinch-off (depleted). At this point, even if VDS still remains, no drain current is created, ie ID=0.

Figure. 9 Schematic Diagram of N-channel Depletion-mode MOS Transistor Structure(left) and Transfer Characteristics(right)

4. The principle of P-channel depletion FET

The P-channel depletion MOS transistor operates in the same way as the N-channel depletion MOS transistor, with the exception that the conductive carriers are different and the supply voltage polarity is likewise different.

5. The difference between depletion mode and enhancement mode MOS tube

The main difference between the depletion and enhancement modes is that the depletion mode MOS tube has a conductive channel when no voltage is applied to the G terminal (Gate), whereas the enhancement mode MOS tube does not have a conductive channel until it is turned on; both modes have a conductive channel. The technique of control is also unique. The depletion MOS tube's VGS (gate voltage) can be turned on using positive, zero, or negative voltage control, however the enhancement MOS tube's VGS>VGS (th) must be achieved (gate threshold voltage) Just go for it.

When VGS=0, the depleted N-channel MOS transistor generates a significant quantity of  Na+  or K+ positive ions in the SiO2 insulating layer (negative ions are doped when the depleted P-channel MOS transistor is manufactured). The electric field can induce enough electrons in the P-type substrate to form an N-type conductive channel; when VGS>0, a substantial ID (drain current) is generated; when VGS0, the positive charge is weakened. The ions create an electric field that narrows the N-channel, lowering the ID.

These characteristics make the depletion-mode MOS tube practical in practical application; when the device is turned on, the MOS tube may be triggered by mistake, resulting in the failure of the entire machine; it is difficult to control, making its application very rare; it is not easy to control, making its application very rare.

As a result, most  NMOS and  PMOS  tubes we see in everyday life are improved MOS tubes;  PMOS can readily be employed as a high-end driver among them. PMOS is frequently replaced by NMOS in high-end drivers due to difficulties with high on-resistance, expensive price, and few replacement kinds. This is also, regardless of application or product type, the most popular cause for upgraded NMOS tubes on the market. Especially in the application of switching power supply and motor drive, NMOS transistors are generally used.

Ⅱ. Important characteristics of MOSFET

1. Conduction characteristics

Conduction is defined as acting as a switch, which is the same as closing the switch. Because of the properties of NMOS, it will be turned on if VGS is greater than a specified value. It can be used when the source is grounded (low-end drive) as long as the gate voltage is between 4 and 10 volts. PMOS has the property of turning on when VGS is less than a particular value, which is ideal for situations when the source is connected to  VCC  (high-end drive).

2. Loss characteristics

After it is turned on, whether it is NMOS or PMOS, there is an on-resistance, and the current will use energy due to the resistance. Conduction loss is the term for this portion of the energy consumed.

When the MOS tube is turned on and off, the voltage at both ends decreases, while the current flowing through it increases. During this time, the MOS tube's loss is equal to the product of the voltage and current, which is referred to as a switch. loss. Switching losses are typically significantly more than conduction losses, and the higher the switching frequency, the more losses.

The loss is proportional to the product of the voltage and current at the instant of conduction. Shortening the switching time lowers the loss per turn-on, while lowering the switching frequency lowers the number of switches per unit time. Switching losses can be reduced using either strategy.

3. Parasitic capacitance driving characteristics

MOS transistors, unlike bipolar transistors, require a higher GS voltage and a faster turn-on speed to be turned on. The parasitic capacitance between GS and GD can be observed in the structure of the MOS tube, and the driving of the MOS tube is theoretically the charging and discharging of the capacitor.

A current is required to charge the capacitor. The instantaneous current will be relatively big since the capacitor can be considered a short circuit at the time of charging. The amount of instantaneous short-circuit current that can be provided is the first thing to consider when selecting/designing the MOS transistor driver; the second thing to consider is that the NMOS, which is commonly used for high-end driving, requires the gate voltage to be greater than the source voltage when it is turned on.

The source voltage is the same as the drain voltage (VCC) when the high-end driven MOS transistor is switched on, therefore the gate turn-on voltage is 4V or 10V higher than  VCC at this time, and the higher the voltage, the faster the turn-on speed and the turn-on duration. In addition, the resistance is reduced.

Figure. 10 Schematic Diagram of the Comparison of the Characteristics of 4 Kinds of MOS Tubes

4. Parasitic diodes

The "body diode," a parasitic diode located between the drain and the source, is primarily utilized for protection loops in applications driving inductive loads (such as motors, relays). The body diode, on the other hand, is found only in a single MOS transistor and is rarely found inside an integrated circuit chip.

Figure. 11 Schematic Diagram of the Position of the Parasitic Diode

5. Characteristics of different pressure-resistant MOS tubes

The resistance ratios of each portion of the on-resistance differ for MOS tubes with varied withstand voltages. For example, the epitaxial layer resistance of a MOS tube with a withstand voltage of 30V is only 29% of the overall on-resistance, whereas the epitaxial layer resistance of a MOS tube with a withstand voltage of 600V is 96.5 percent.

The fundamental difference between voltage-resistant MOS tubes is that high-voltage MOS tubes have a slower response speed than low-voltage MOS tubes. As a result, changes in their characteristics can be seen in actual applications such as medium and low voltage MOS tubes. To match the strong current and high power processing capability, the tube only requires a very low gate charge. The high-voltage MOS tube has an input impedance, in addition to its fast switching speed. It also has minimal switching loss, making it ideal for  PWM  output mode applications. It is frequently utilized in electronic ballasts, electronic transformers, and switching power supplies due to its high features.

Ⅲ. The difference between MOSFET and triode, IBGT

1. The difference between MOS tube and triode

The semiconductor triode's principal function is to magnify the little signal. MOS tubes and triodes have a lot in common, but they also have a lot of differences. The first is the pace at which the switches are turned on and off. Both PN junctions will induce charges when the triode is operational. The triode is in a saturated state when the switch is turned on. If the triode is turned off at this point, the charge produced by the PN junction must be brought back to equilibrium. This is a lengthy procedure. MOS, on the other hand, can be employed as a high-speed switch due to its various functioning mechanisms and lack of recovery time.

The second point to consider is the various control methods.The triode is a current control element, while the MOS tube is a voltage control element. When the signal voltage is low and more current is allowed from the signal source, the MOS tube should be chosen; when the signal voltage is high and more current is allowed from the signal source, the triode should be chosen.

The difference in the number of carrier species comes next. The term "unipolar device" in power electronic technology refers to a device that conducts electricity using only one type of carrier, whereas "bipolar device" refers to a device that uses two types of carriers to conduct electricity. The MOS tube is also known as a unipolar device since it only uses one type of majority carrier conduction, whereas the triode uses both majority and minority carriers for conduction, making it a bipolar device.

The third factor is adaptability. Some MOS tubes' source and drain can be used interchangeably, and the gate voltage can be positive or negative, making them more versatile than triodes.

The fourth point to consider is the various integration capabilities. MOS tubes are frequently employed in large-scale integrated circuits because they can operate at very low current and voltage, and their manufacturing technique allows for the easy integration of multiple MOS tubes on a silicon wafer.

The difference in input impedance and noise capability is the sixth factor. MOS tubes are commonly utilized in electronic devices because of their high input impedance and low noise. MOS tubes, especially when employed as the input stage of the entire electronic device, can attain performance that is impossible to achieve with regular triodes.

Finally, there is a difference in power use. When utilizing a MOS tube, the power loss is modest; but, when employing a triode, the power loss is substantially higher.

MOS tubes are, of course, more expensive to operate than triodes. MOS tubes are frequently used in high-frequency high-speed circuits, high-current places, and central areas that are sensitive to base or drain control currents, based on the characteristics of the two components; the triode is used in low-cost places, and when the effect is not achieved, it will be considered to replace the MOS tube.

2. The difference between MOS tube and IBGT

Insulated Gate Bipolar Transistor (IGBT) is a voltage-driven power semiconductor device made up of  BJT  (Bipolar Transistor) and MOS Insulated Gate Field Effect Transistor. The advantages of both the input impedance and the power transistor's reduced on-voltage drop (GTR).

The  GTR  saturation voltage is lowered, but the current carrying density is high, and the driving current is high; the MOSFET  driving power is low, but the switching speed is quick, but the on-state voltage drop is considerable, and the current carrying density is low. The advantages of the preceding two devices are combined in the IGBT, which has a low driving power and lower saturation voltage.

Single-tube and module IGBTs are the two most common varieties. A single-tube has a look that is comparable to that of a MOS tube.  Fuji Electric , Fairchild Semiconductor  , and others are common manufacturers. Internally, the module products usually enclose many single IGBTs that are coupled into a suitable circuit.

Because the IGBT operates on the concept of turning on the MOS tube first and then driving the triode to turn on, the switching speed of the IGBT is slower than that of the MOS tube but faster than that of the triode.

IGBTs have a substantially greater production cost than MOS tubes. This is due to the fact that IGBT manufacture requires extra processes such as ion implantation on the back of the wafer and low-temperature annealing of the wafer (such as laser annealing), both of which necessitate the employment of expensive wafer-processing machines.

Low-voltage MOS tubes' conduction voltage drop is typically kept below 0.5V (generally no more than 1V), such as the IR4110 low-voltage MOS tube, which has an internal resistance of 4m and a conduction current of 100A to switch on. The voltage drop is approximately 0.4 volts. The fact that the current conduction voltage is reduced indicates that the conduction loss is negligible, and it also has low switching loss characteristics. As a result, the IGBT has no electrical performance advantage over the MOS tube, and the MOS tube has higher cost performance advantages, making the low voltage IGBT virtually impossible to observe.

The major disadvantage of MOS tubes is that when the withstand voltage rises, the internal resistance rises as well, resulting in a very high internal resistance under high pressure, preventing MOS tubes from being used in high-power applications.

Although the MOS tube has the fastest switching speed in the high-voltage field, the turn-on voltage drop of the MOS tube under high pressure is very substantial (the internal resistance increases rapidly with the increase of the withstand voltage). The on-resistance of a COOLMOS tube with a withstand voltage of 600V can be several ohms, resulting in a relatively limited current withstand.

However, the on-voltage drop of IGBT does not grow much at high withstand voltage (the on-current of IGBT is processed by triode), therefore IGBT has evident advantages at high voltage, not only in terms of switching speed but also in terms of triode current characteristics; The switching speed of the latest generation of IGBT devices is high (nanosecond level), and the on-state voltage drop, switching loss, and other parameters have improved significantly, making the IGBT more resistant to pulse current impact and offering high withstand voltage and low driving power. more noticeable

MOS tubes have virtually no advantages under scenarios where a withstand voltage of more over 150V is required. When the typical IRFS4115 and the fourth-generation IGBT type SKW30N60 are compared under 150V, 20A continuous operating conditions, the former has a switching loss of 6mJ/pulse, while the latter has a switching loss of only 1.15mJ/pulse, which is less than 1/5 of the former; under working conditions, the power load difference between the two will be even greater!

MOS tubes are currently uncommon in high-power areas such as metallurgy, steel, high-speed railroads, and ships, while IGBT components are commonly employed.

In general, IGBTs are better suited to environments with high voltage, high current, and low frequency (about 20 kHz). The more advantages IGBT has, the greater the voltage. The advantage of IGBT is clear above 600 volts; in the field of current and low frequency (tens of KHz to several MHz), the lower the voltage, the better the MOS tube.

Ⅳ. Main parameters of MOSFET

The FET has many parameters, including limit parameters, dynamic electrical characteristic parameters, and static electrical characteristic parameters, with the following being the most important: saturation drain-source current IDSS, pinch-off voltage Up, turn-on voltage VT (reinforced insulating gate tube), cross  Conductive gM , drain-source breakdown voltage  BVDS , maximum dissipation power PDSM, and maximum drain-source current IDSM, among others.

1. Maximum rated parameters

The maximum rated parameters require all values to be obtained under the condition of Ta=25℃.

VDS/VDSS maximum drain-source voltage

The drain-source rated voltage VDSS [also written as V(BR)DSS] refers to the highest voltage that can be supplied before the drain-source avalanche breakdown occurs in a gate-source short circuit. The actual avalanche breakdown voltage may be lower than the specified VDSS depending on temperature.

VGS/ VGSS Maximum Gate-Source Voltage

The maximum voltage that can be applied between the gate and source is determined by the VGS [or V(BR)GSS] voltage rating. The major goal of setting this rated voltage is to prevent excessive voltage from damaging the gate oxide  layer. The real gate oxide  can handle much more voltage than the specified voltage, but this varies according on the manufacturing process, therefore maintaining the VGS within the stated voltage can help ensure the application's stability.

ID Continuous leakage current

When the chip is at the highest rated junction temperature TJ(max) and the tube's surface temperature is 25°C or above, ID is defined as the maximum permitted continuous  DC  current. The rated thermal resistance RJC between the junction and the case, as well as the case temperature, determine this parameter:

ID does not account for switching losses, and it is difficult to hold the tube surface temperature at 25°C (Tcase) in practice. As a result, the actual switching current in hard-switching applications is often 1/3 to 1/4 of the ID rating at TC=25°C.

Note: The thermal resistance JA can be used to estimate the ID at a certain temperature, and this number is more realistic.

IDM/IDSM pulsed drain current/maximum drain-source current

This value represents the device's ability to handle pulsed current, which is substantially higher than continuous  DC current. The ohmic area of the line is the reason for defining the IDM. After the MOSFET  is turned on, there is a maximum drain current for a given gate-source voltage, as shown in Figure 15. If the operating point is in the linear zone for a given gate-source voltage, the increase in drain current will be linear. Conduction losses are increased as the drain-source voltage is increased. Working at a high power level for an extended period of time will lead the gadget to fail. As a result, the nominal IDM must be set below the region defined by the intersection of VGS and the curve for normal gate driving voltages.

Figure. 16 After the MOSFET is Turned on, There is a Maximum Drain Current

As a result, the top limit of the current density must be established to avoid the chip from being burned owing to high temperatures. This is primarily to prevent excessive current flow through the package leads, as the package leads are sometimes the "weakest connection" across the chip.

The temperature rise is dependent on pulse width, time interval between pulses, heat dissipation conditions, RDS(on), and pulse current waveform and amplitude, all of which are limited by thermal effects on IDM. Simply ensuring that the pulse current does not exceed the IDM's upper limit does not ensure that the junction temperature stays below the maximum permitted value. Refer to the discussion of instantaneous thermal resistance in Thermal and Mechanical Properties to estimate the junction temperature under pulsed current.

PDSM maximum power dissipation

At a case temperature of 25°C, the total allowed channel power dissipation, which scales the device's maximum power dissipation, can be expressed as a function of the maximum junction temperature and thermal resistance.

Operating temperature ranges for TJ and TSTG, as well as storage ambient temperature ranges

For the device's operation and storage environments, these two values define the permissible junction temperature range. This temperature range was chosen to meet the device's minimum functioning life requirements. The device's operating life will be substantially extended if it works within this temperature range.

EAS single-pulse avalanche breakdown energy

The device will not undergo avalanche breakdown if the voltage overshoot value (typically owing to leakage current and stray inductance) does not exceed the breakdown voltage, hence the ability to dissipate avalanche breakdown is not necessary. Avalanche breakdown energy is a term that describes a safe level of transient overshoot voltage that a device can sustain, and it is determined by the amount of energy that must be lost for avalanche breakdown to occur.

A device that specifies a rated avalanche breakdown energy almost always specifies a rated EAS as well. The terms rated avalanche breakdown energy and rated  UIS  are interchangeable. EAS determines how much reverse avalanche breakdown energy a gadget can safely sustain.

L denotes the inductance value, while ID denotes the peak current flowing through the inductance, which translates to the measurement device's drain current. Avalanche breakdown occurs when the voltage created on the inductor surpasses the MOSFET  's breakdown voltage. Even when the MOSFET  is turned off, the inductor current flows through the device due to avalanche breakdown. The energy held in the inductor is similar to the energy dissipated by the MOSFET  from the stray inductance.

It's challenging to get the same breakdown voltage between multiple devices after MOSFET  s are coupled in parallel. A gadget is usually the first to experience avalanche breakdown, and all of the avalanche breakdown current (energy) then flows through it.

EAR Repeating  Avalanche Energy 

The "industry standard" for repetitive avalanche energy has become the "industry standard," although this parameter is meaningless without a specified frequency, additional losses, and cooling. Avalanche energy is frequently limited by heat dissipation (cooling) conditions. It's also impossible to forecast how much energy an avalanche will generate.

The primary purpose of the rated  EAR  is to define the device's ability to sustain recurrent avalanche breakdown energy. The premise of this concept is that the frequency has no limit so long as the device does not overheat, which is true for any device that can experience avalanche breakdown. It is best to measure the temperature of the device or heat sink in operation while evaluating the device design to see if the  MOSFET  device is overheating, especially for devices that may exhibit avalanche breakdown.

IAR avalanche breakdown current

The tendency of on-chip current to pool during avalanche breakdown necessitates restricting the avalanche current IAR for particular devices. The avalanche current becomes a "fine articulation" of the avalanche breakdown energy specification in this way, revealing the device's full capabilities.

Figure. 17 Circuit and Waveform of Avalanche Damage Endurance Test

SOA Secure Workspace

The safe operating area of each MOS transistor is simply defined as the power dissipation when the junction temperature reaches the maximum allowable value. Because the power MOS transistor does not show secondary breakdown, the safe operating area is simply defined as the power dissipation when the junction temperature reaches the maximum allowable value.

2. Static electrical characteristics

V(BR)DSS/VBDSS Drain-source breakdown voltage (destruction voltage)

The drain-source voltage, also known as BVDS, occurs when the current flowing down the drain reaches a certain value at a certain temperature and the gate-source short circuits. The avalanche breakdown voltage is the drain-source voltage in this scenario.

The maximum drain-source voltage rating of V(BR)DSS lowers with temperature since it has a positive temperature coefficient. V(BR)DSS is about 90 percent of the highest drain-source voltage rating at 25°C at -50°C.

BVGS gate-source breakdown voltage

In the process of increasing the gate-source voltage, the VGS when the gate current IG starts to increase sharply from zero.

VGS(th) threshold voltage

It's also denoted as VT, which denotes the voltage at which the drain begins to have current, or the voltage at which the current disappears when the  MOSFET is turned off. The test circumstances are also stated (drain current, drain-source voltage, and junction temperature). Normally, the threshold voltages of all MOS gate devices are different. As a result, the VGS(th) variation range is provided. Because VGS(th) has a negative temperature coefficient, the MOSFET will turn on at a lower gate-to-source voltage as the temperature rises.

VGS(off) pinch-off voltage

It's also known as Up, which refers to the gate voltage in a junction or depletion type insulated gate field effect transistor when the drain and source are just switched off.

RDS(on) On-resistance

At a set drain current (typically half of the ID current), gate-source voltage, and 25°C, the drain-source resistance is measured.

RGS gate-source resistance

This characteristic is sometimes illustrated by the gate current flowing through the gate, and the RGS of the MOS tube can easily reach 1010Ω.

IDSS zero gate voltage drain current

The leakage current between the drain and source at a certain drain-source voltage when the gate-source voltage VGS=0 is also known as saturated drain-source current. IDSS is defined at both room temperature and increased temperature since leakage current increases with temperature. The leakage current's power dissipation can be estimated by multiplying IDSS by the voltage between the drain and source, and this portion of the power dissipation is normally neglected.

IGSS gate-source drain current

At a given gate-source voltage, this is the leakage current passing through the gate.

3. Dynamic electrical characteristics

Ciss input capacitance

The drain-source is shorted, and the capacitance measured with an  AC  signal between the gate and the source is the input capacitance. Ciss is made up of the gate-drain and gate-source capacitances Cgd and Cgs in parallel, or Ciss=Cgs+Cgd. The device may be switched on when the input capacitor is charged to a threshold voltage, and it can be turned off when the input capacitor is drained to a particular value. As a result, the drive circuit and Ciss have a direct influence on the device's turn-on and turn-off delays.

Coss output capacitor

The gate-source is shorted, and the output capacitance is determined by measuring the capacitance between the drain and source with an  AC signal. The drain-source capacitance Cds and the gate-drain capacitance Cgd are connected in parallel to form Coss, or Coss=Cds+Cgd. Coss is critical in the use of soft switching since it can cause the circuit to resonate.

Crss reverse transfer capacitor

The reverse transfer capacitance is the measured capacitance between the drain and gate when the source is grounded. The gate-to-drain capacitance is equal to the reverse transfer capacitance. The reverse transfer capacitance, also known as Miller capacitance, is one of the most important parameters for the rise and fall time of the switch, and it also affects the turn-off delay time. Cres=Cgd is one of the most important parameters for the rise and fall time of the switch, and it also affects the turn-off delay time. Capacitance reduces when the drain-source voltage rises, particularly the output and reverse transfer capacitances.

Eoss output capacitor stores energy

The output capacitor Coss in the MOS tube stores a certain amount of energy. The output capacitance Coss of a MOS tube changes with the change in VDS voltage since it has very visible nonlinear features. If the Datasheet has this parameter, it will be very useful in determining the MOS tube's switching loss. This parameter is not included in all MOS tube manuals, and it is absent from the majority of Datasheets.

di/dt current rate of rise

The reverse recovery properties of the MOSFET body diode are represented by this parameter. The charge storage affects the diode because it is a bipolar device. The charge held in the PN junction must be released when the diode is reverse biased, and the aforementioned characteristics represent this property.

Qgs,  Qgd  and Qg (gate charge value)

The charge stored on the capacitor between the terminals is reflected by the Qg gate charge value, also known as the total gate charge. The gate drive circuit is frequently constructed to account for the gate effect of electric charge since the charge on the capacitor changes with the voltage at the time of switching.

Qgs is the charge from 0 to the first inflection point,  Qgd is the charge from the first inflection point to the second inflection point (also known as the "Miller" charge), and Qg is the charge from 0 to VGS, which corresponds to a specific drive section of the voltage.

The gate charge value is unaffected by changes in drain current or drain-source voltage, and the gate charge does not change with temperature. The conditions of the test are provided. The datasheet includes a graph of the gate charge, which includes the gate charge curve for a fixed drain current and a variable drain-source voltage. The plateau voltage VGS(pl) climbs just slightly as the current increases in the figure above (and decreases as the current decreases). Because the plateau voltage is proportional to the threshold voltage, the plateau voltage will vary depending on the threshold voltage. Details can be seen in the diagram below:

td(on) turn-on delay time

is the time elapsed from when the gate-source voltage rises to 10% of the gate drive voltage to when the drain current rises to 90% of the specified current.

td(off) turn-off delay time

is the time from when the gate-source voltage drops to 90% of the gate drive voltage to when the drain current drops to 10% of the specified current. This shows the delay experienced before the current is delivered to the load.

Tr rise time

Rise time is the time it takes for the drain current to rise from 10% to 90%.

Tf fall time

The fall time is the time it takes for the drain current to drop from 90% to 10%.

NF low frequency noise figure

The decibel is the measurement unit (dB). The noise is created by the movement of the carriers inside the tube being uneven. Even if there is no signal input, the amplifier will have an uneven voltage or voltage at the output due to its presence. a current shift The noise generated by the tube is proportional to the noise figure NF value. The FET has a noise figure of several decibels, which is lower than that of a bipolar transistor.

gM transconductance

It is an important parameter to weigh the amplification ability of the gate-source voltage VGS to the drain current ID, that is, the ratio of the change of the drain current ID to the change of the gate-source voltage VGS.