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Hello everyone, I am Rose. Welcome back to the new post today. The fact that electrons never stay in one place and must return no matter where the current runs are one of the properties of electron flow. As a result, current flows in the loop at all times, and any signal in the circuit exists as a closed-loop.
A digital signal propagates from one logic gate to the next in the schematic layout of a digital circuit. The signal is sent over a wire from the output to the receiving end. It appears to be flowing in only one way. As a result, many digital engineers believe the loop path is unrelated.
After all, both the driver and the receiver are voltage-mode devices, so why take current into account?
In actuality, the signal is conveyed by current, specifically the movement of electrons, according to basic circuit theory. The fact that electrons never stay in one place and must return no matter where the current runs are one of the properties of electron flow. As a result, current flows in the loop at all times, and any signal in the circuit exists as a closed-loop.
It is actually a method of charging the dielectric capacitor sandwiched between the transmission line and the DC layer for high-frequency signal transmission.
Ground and power planes are typically used to complete the reflow in digital circuits. High-frequency frequencies and low-frequency signals have various return routes. Select the path with the lowest impedance for low-frequency signal return and the path with the lowest inductance for high-frequency signal return.
There is always a return current in the opposite direction when current starts from the signal driver, flows through the signal line and is injected into the signal receiving end: starting from the ground pin of the load, passing through the copper plane, flowing to the signal source, and flowing through the signal receiving end. A closed-loop is formed by the current on the signal line.
The signal frequency is equal to the noise frequency created by the current flowing through the copper-clad plane. The frequency of the signal is proportional to the frequency of the noise.
The logic gate responds to the difference between the input signal and the reference pin, rather than the absolute input signal. The difference between the incoming signal and its logical ground reference plane triggers the single-point termination circuit. As a result, both ground reference plane disturbance and signal path interference are equally essential. The logic gate responds to the input pin and the designated reference pin, and we don't know which one is which (for TTL, it's usually a negative power supply; for ECL, it's usually a positive power supply, but not all of them). In terms of this property, the differential signal's anti-interference ability can reduce ground bounce noise and power plane sliding.
Due to the existence of the power wire and the ground wire, when multiple digital signals on the PCB are switched synchronously (such as the CPU data bus, address bus, and so on), transient load current flows from the power supply into the circuit or from the circuit into the ground wire. Impedance causes synchronous switching noise (SSN), as well as ground plane bounce noise (also known as a ground bounce) on the ground line. When the power line and ground line on the printed board has a greater surrounding region, their radiated energy is also larger.
As a result, we examine the digital chip's switching status and take steps to manage the reflow mechanism in order to achieve the goal of reducing the surrounding area and lowering the degree of radiation.
for example:
The signal output terminal is IC1, the signal input terminal is IC2 (the receiving terminal is supposed to have a downstream resistor to simplify the PCB model), and the ground layer is the third layer. Both IC1 and IC2's ground planes are from the third ground plane. A power plane connects the positive pole of the power supply to the upper right corner of the TOP layer. The decoupling capacitors of IC1 and IC2 are C1 and C2, respectively. The power supply and ground pins of the chip depicted in the diagram correspond to the signal sending and receiving ends' power supply and ground.
If the S1 terminal produces a high level at low frequencies, the whole current loop is that the power supply is linked to the VCC power plane by a wire, then enters IC1 via the orange path, exits the S1 terminal, and enters IC2 via the second layer of the wire via the R1 terminal. Then, via the red channel, enter the GND layer and return to the negative pole of the power supply.
The signal will be greatly influenced by the distribution properties of the PCB at high frequencies. The ground return, which we frequently discuss, is a common problem in high-frequency communications. When the current in the signal line is increased from S1 to R1, the external magnetic field changes rapidly, causing a reverse current to flow in surrounding conductors. If the third layer's ground plane is a complete ground plane, a current will be generated on the ground plane, as represented by the blue dashed line. There will be a return flow along the blue dashed line on the TOP layer if the TOP layer has a complete power plane. At this point, the signal loop has the lowest current loop, the smallest amount of energy emitted to the outside, and the smallest ability to couple external signals. The skin effect is the smallest outward radiation energy at high frequencies, and the concept is the same.
The chip is powered by the decoupling capacitor closest to the chip since the high-frequency signal level and current vary rapidly but with a brief change time, therefore the energy required is not particularly high. The orange path on the top layer and the red path on the GND layer can be considered nonexistent when C1 is large enough and the response is rapid enough (with a very low ESR value) (there is a current corresponding to the power supply of the entire board, but Not the current corresponding to the signal shown in the figure).
As a result, the whole course of the current, according to the environment depicted in the diagram, is: from the positive pole of C1 to the VCC of IC1 to the signal line of S1 to L2 R1 to the GND of IC2 to the yellow path of the GND layer to the via to the negative electrode of the capacitor.
In the vertical direction of the current, there is a brown equivalent current, and a magnetic field will be induced in the middle. This torus can easily link to an external disturbance at the same time.
If the signal in the diagram is a clock signal, a set of 8bit data lines are connected in parallel, powered by the same chip's power supply, and the current return path is the same.
A strong reverse current will be induced on the clock if the data line level flips in the same direction at the same moment. This crosstalk is enough to kill the clock signal if the clock line isn't properly matched. The strength of this type of crosstalk is proportional to the current change rate of the interference source, not to the absolute value of the high and low levels of the interference source. The crosstalk current is proportional to: dI/dt=dV/(T10% -90% *R) for a purely resistive load.
The parameters of the interference source are dI/dt (rate of current change), dV (swing amplitude of the interference source), and R (load of the interference source) in the formula. When dealing with a capacitive load, dI/dt is inversely proportional to the square of T10% -90%.
Low-frequency signals may not have less crosstalk than high-speed communications, as the calculation shows. That is to say, a 1KHz signal is not always a low-speed transmission; we must examine the entire condition at the edge. A signal with a steep edge has a large amplitude at each frequency multiplication point and contains a lot of harmonic components.
As a result, you should be cautious when choosing devices. Choose chips with quick switching speeds with caution. Not only will the cost be prohibitively high, but it will also exacerbate crosstalk and EMC issues.
Any nearby power plane or another plane can be used as the return plane of this signal as long as there is an appropriate capacitor on both ends of the signal to provide a low-reactive path to GND. The corresponding chip IO power supply for sending and receiving is often the same in normal applications, and there are usually 0.01-0.1uF decoupling capacitors between each power supply and ground, and these capacitors are also at the two ends of the signal, so the power plane's reflow effect is second only to the ground plane's. When additional power planes are used for return flow, however, there is rarely a low reactance path to the ground on both ends of the signal. The current produced in the neighboring plane will then find the capacitance closest to it and return to the ground. If the "nearest capacitor" is distant from the start or end, the return must travel a considerable distance to make a complete return path, and this path also serves as a return path for adjacent signals. Road and common ground interference have the same effect, which is similar to signal crosstalk.
A high-pass filter (such as a 10-ohm resistor string 680p capacitor) produced by a capacitor or RC series connection (such as a 10 ohm resistor string 680p capacitor) can be attached across the divide for some unavoidable cross-supply divisions. The exact value is determined by the type of signal, i.e., to offer a high-frequency return path while still isolating low-frequency crosstalk between mutual planes). This may entail the challenge of putting capacitors between the power planes, which is amusing at first but very effective. If some standards prohibit it, you can connect capacitors to the ground on the two division planes.
It is recommended to connect a few tiny capacitors to the ground at both ends of the signal to provide a return path when borrowing other planes for return flow. However, this strategy is frequently difficult to implement. Because the chip's matching resistor and decoupling capacitor take up the majority of the surface area at the terminal.
On the reference plane, return noise is one of the most common sources of noise. As a result, the return current's course and flow range must be investigated.
A circuit on the printed board is depicted in the image below. A current is flowing across the wire. On the surface, we usually only see the cable that transmits the signal. In fact, the current is always in from the driver to the receiver. It can only flow in one direction: around the loop. We can see the transmission line, but the direction of the current return is usually hidden. They typically return through the earth and power planes. The loop path is difficult to estimate because there is no actual line. They are tough to regulate to a certain extent.
Each wire and its loop on the PCB form a current loop, as shown in Figure 3.1. When a sudden current passes through a wire loop in a circuit, an electromagnetic field is formed in space that affects neighboring wires, according to the principle of electromagnetic radiation. Radiation is the term used to describe the act of causing an impact. To limit the influence of radiation, we must first comprehend the fundamental principles of radiation as well as the characteristics associated with radiation intensity.
Figure 3.1 Differential Mode Radiation on Printed Boards
These loops are similar to miniature antennas that radiate magnetic fields into space while they are in use. To imitate it, we use the radiation produced by a tiny loop antenna. With current, I and area S, create a tiny loop. In free space, the electric field strength measured in the distant field of r is:
Equation 3.1 is appropriate for a tiny ring placed in a free region with no surface reflection. In fact, rather than a free place, our product is carried out on the ground. The measured radiation will be increased by 6dB due to reflection from the neighboring ground. Equation 3.1 must be multiplied by 2 in order to account for this. If the ground reflection is rectified and the highest radiation direction is considered, the formula 3.1 is as follows:
Radiation is proportional to the loop current and loop area, and proportional to the square of the current frequency, according to equation 3.2.
The frequency of the current is closely related to the course of the return current in the printed circuit board. DC or low-frequency current always flows in the direction of least impedance, but high-frequency current always flows in the direction of least inductive reactance with a specified resistance, according to basic circuit understanding.
If the vias' holes and trenches on the copper-clad plane aren't taken into account, the path with the lowest impedance, i.e. the path of low-frequency current, is made up of arc lines on the copper-clad plane, as illustrated in Figure 3.2. The resistivity of each arc is related to the current density on that arc.
Figure 3.2 High-Frequency Current Path on PCB Copper Plane
As illustrated in Figure 3.3, the return path with the lowest inductance, i.e. the return path for high-frequency current, is on the copper plane directly beneath the signal wiring. This return path reduces the amount of space encircled by the loop, as well as the magnetic field strength (or ability to receive space radiation) that the loop antenna generated by this signal radiates into space.
It can be considered an appropriate transmission line for moderately long, straight wiring. It propagates signal return current via a band-shaped area with the signal wiring as the center axis. The current density decreases as the distance from the signal wiring's central axis increases.
As depicted in Figure 3.3. formula 3.3 is approximately satisfied by this relationship:
formula3.3
Figure 3.3 Transmission Line Returns Current Density Distribution Map
Table 3.1 shows the proportion of return current flowing through the belt-shaped region with the transmission line's center and width as the center and width, according to formula 3.3.
Table3.1 The Proportion of Return Current Flowing
According to formula 3.3, Table 3.1 depicts the proportion of return current flowing through the belt-shaped region with the transmission line's center and width as the center and width.
The noise interference of the signal return current to the copper-clad plane is local when there is a continuous, dense, and complete copper-clad plane under the signal wiring. As long as the principle of layout and wiring localization is followed, that is, the distance between digital signal lines, digital devices, and analog signal lines, and analog devices is artificially extended to a certain extent, the impact of digital signal return current on analog circuits can be greatly reduced. interference.
The high-frequency transient return current flows back to the drive end via the plane adjacent to the signal trace (ground plane or power plane). The driver signal trace's terminal load is connected across the signal trace and the plane (ground plane or power plane) directly adjacent to it.
The radiation energy of the power line and ground line on the printed board increases as their surrounding region grows larger. As a result, by limiting the return path and hence the degree of radiation, we may reduce the surrounding region.
Chip connections, copper surface cutting, and via jump are the three most common causes of reflow difficulties on PCBs. The following is a detailed examination of these variables.
4.1 Reflow problems caused by chip interconnection
When the digital circuit is turned on, the voltage is converted from high to low, causing a transient load current to flow from the power source to the circuit or from the circuit to the ground.
The pin input resistance of digital devices can be considered infinite, which is the same as an open circuit I = 0 in the diagram below). The loop current is actually generated by the chip, power supply, and ground plane's distributed capacitance and distributed inductance. return. As an example, the collector output circuit is used as the internal circuit of the output signal in the following analysis.
4.1.1 Drive end changes from low level to high level
When the output signal goes from low to high, it's the same as the output pin sending electricity through the transmission line. We believe that no current flows in from the input tube leg for the chip because of the infinite input resistance. The current must return to the output chip's power pin.
①Signal traces are close to the power plane
The current enters the device from the power supply pin of the drive and flows from the output end of the drive to the load end; the high-frequency transient return current flows back to the output terminal of the driver on the power plane below the signal trace, and the return current directly passes through the power plane, entering the driver from the power supply pin of the drive and flowing from the output end of the drive to the load end;
②The signal trace is close to the ground plane
The current enters the device from the power pin of the driver and flows from the output end of the driver to the load end; the driver charges the transmission line formed by the signal trace, the power plane, and the terminal load; the current enters the device from the power pin of the driver and flows from the output end of the driver to the load end;
Below the signal trace, the high-frequency transient return current flows back to the driver's output terminal on the ground plane. To cross from the ground plane to the power plane and then from the driver's output terminal, the return current must use the coupling capacitor between the power plane and the ground plane. A current loop is formed when the driver's power supply pin enters the driver.
4.1.2 Drive end changes from high level to low level
It is equivalent to the output pin absorbing the current on the transmission line.
① Signal traces are close to the power plane
The transmission line created by the signal trace, the power plane, and the driver's output terminal is discharged by the load. The current enters the device via the driver's output pin, flows out of the driver's ground pin, enters the ground plane, and passes through the power near the driver's ground pin. High-frequency transient return current flows back to the load end on the power plane under the signal traces, generating a current loop. The plane and ground plane coupling capacitors cross to the power plane and return to the load end.
② The signal trace is close to the ground plane
The load discharges the transmission line formed by the signal trace, the power plane, and the driver's output terminal, and current flows into the device from the driver's output pin, out of the ground pin, into the ground plane, and back to the load end; high-frequency transient return current Form a current loop by returning to the load end on the ground plane below the signal trace.
The coupling capacitor between the power plane and the ground plane should be located between the driver's output pin and ground pin to provide a return channel for the return current. Otherwise, for return flow, the return current will locate the shortest coupling path between the power plane and the ground plane ( Makes the return path difficult to predict and control, causing crosstalk to other traces).
4.2 Solutions to reflow problems caused by copper-clad cutting
The voltage loss caused by resistance can be reduced by using a ground plane and a power plane. The loop current returns to the ground, as illustrated in the diagram. A voltage drop will definitely occur at points 1 and 2 due to the presence of the resistor R1. The greater the resistance, the larger the voltage drop, resulting in ground level discrepancies. It is possible that there is a ground layer. It's a signal line with an infinite line width and a low resistance. The ground layer closest to the signal always receives the loop current. If the signal lies between two ground planes that are identical, the loop current will pass through both planes equally when there are more than one layer in the ground.
4.2.1 Under the condition of localization of layout and wiring,
The analog ground plane and the digital ground plane share the same copper-clad plane, so there is no differentiation between the digital and analog grounds, and the noise from the digital circuit will not add to the noise from the analog circuit system.
4.2.2 In the digital and analog mixed circuit system,
Because the common location of the digital ground and the analog ground is chosen outside the board, the two copper planes are completely independent, and the signal line between the digital and analog circuits lacks the characteristics of a transmission line, causing serious signal integrity issues in the system. The ground plane is not split, and the digital and analog circuits share the same power system. The digital circuit module and the analog circuit module share a complete circuit in the architecture of the digital and analog mixed circuit system, which is based on the modular layout and localized wiring. The undivided voltage reference plane not only prevents digital circuitry from interfering with analog circuits, but also removes the problem of the signal line "cross-channel," which can considerably minimize signal crosstalk and system ground bounce noise. The front-end analog circuit's precision has been increased.
4.3 Solutions to backflow problems caused by vias
Many signals must be modified in the signal wiring of the printed board if it is a multilayer board to finish the connecting task. A huge number of vias are being used at this moment. Vias have two effects on reflow: the first is vias. The first is the reflow jump layer flow induced by the via hole, which is blocked by a trench.
4.3.1 Trenches formed by vias
Many signals must be modified in the signal wiring of the printed board if it is a multilayer board to finish the connecting task. A huge number of vias are being used at this moment. When vias are densely packed in the power or ground plane, multiple vias may be joined together to form a so-called groove, as illustrated in the figure. First and foremost, we must assess the circumstances to determine whether the reflow must travel through the trench. The signal reflow will not be hampered if it does not have to pass through the trench.The antenna effect created will quickly grow if the loop circuit bypasses this groove and returns, causing interference to surrounding signals. After the coating data is obtained, we can usually correct the spots where the vias are too dense and the trenches are formed so that a specified spacing is left between the vias.
4.3.2 Layer jump phenomenon formed by vias
For the purposes of study, we'll use a six-layer board as an example. Two coating layers are on the six-layer board, the ground layer is on the second layer, and the power layer is on the fifth layer. As a result, the surface layer and third layer signal reflow is primarily in the ground layer, whereas the bottom and fourth layers signal reflow is primarily in the power layer.
When it comes to layer wiring, there are six options:
Surface layer <-> third layer
Surface layer<->Fourth layer
Surface layer<->Bottom layer
Third floor <-> fourth floor
The third layer <-> bottom layer
Fourth floor<->Bottom
According to the loop current, the six probable scenarios can be split into two categories: loop current flows on the same layer and on distinct layers, indicating whether there is a layer hop phenomenon.
①When the loop current flows on the same layer
The surface layer becomes the third layer, while the fourth layer becomes the bottom layer.
The loop current flows on the same layer in this situation. The internal electric field strength of a full conductor in an electric field, on the other hand, is zero, and all currents flow on the conductor's surface, according to the concept of electrostatic induction. The power supply and the ground plane The plane is one of these conductors.
All of the vias that we use are through holes. When these vias pass through the power supply and ground plane, holes are created that allow current to flow between the upper and lower surfaces of the coating layer. As a result, the signal lines' return path is excellent. There is no need to take steps to improve.
②The situation where the loop current flows on different layers
Surface layer-> fourth layer, surface layer-> bottom layer, third layer-> fourth layer, and third layer-> bottom layer are all examples.
To examine the reflow issue, consider the surface layer->bottom layer and the third layer->fourth layer cases.
To provide a return channel for signals with layer jump phenomenon, some bypass capacitors near the dense area of vias, usually 0.1uf magnetic chip capacitors, must be added.
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