Flip-flop is an electronic component that can store the state of a circuit. The memory cell circuit that can only act when triggered by a clock signal is called a flip-flop to distinguish latches that are not controlled by a clock signal.

Ⅰ Introduction

Flip-flop is an electronic component that can store the state of a circuit. The simplest one is an RS flip-flop composed of two NOR gates, two input terminals, and two output terminals (see Figure). The more complicated ones are D flip-flops with clock (CLK) segment and D (Data) terminal, which follow the state of D terminal when CLK terminal is high level and latch the signal at the moment when CLK terminal becomes low level. More commonly used is the edge D flip-flop, which is formed by cascading two simple D flip-flops and latches the signal at the edge of the clock. It is widely used in electronic components such as counters, arithmetic units, and memories.

The actual digital system contains a large number of memory cells, and they are often required to act in synchronization at the same time. To achieve this goal, a clock pulse (CLK) is introduced as a control signal on each memory cell circuit. Only when CLK comes, the circuit is "triggered" to act, and change the output state according to the input signal. This kind of memory cell circuit that can only act when triggered by a clock signal is called a flip-flop to distinguish latches that are not controlled by a clock signal.

RS flip-flop

Ⅱ Types

Logic function refers to the logical relationship between the secondary state and the current state of the flip-flop and the input signal in the steady-state. This logical relationship can be given by a characteristic table, characteristic equation, or state transition diagram. According to the different characteristics of logic functions, the flip-flops are divided into RS, JK, T, D, and other types.

Circuit structure refers to the type and combination of gate circuits in the circuit. Basic RS flip-flop, synchronous RS flip-flop, edge flip-flop, etc. refer to different forms of the circuit structure. Due to the different circuit structures, different action characteristics are brought. The flip-flops of the same logic function can be realized with different circuit structures. Conversely, the same circuit structure can be used as flip-flops with different logic functions.

According to logic functions: RS flip-flop, D flip-flop, JK flip-flop, T flip-flop.

According to trigger modes: level flip-flop, edge flip-flop, and pulse flip-flop.

According to the circuit structure: basic RS flip-flop and clock-controlled flip-flop.

According to the principle of storing data: static flip-flop and dynamic flip-flop.

According to the basic devices constituting the flip-flop, it is divided into bipolar flip-flop and MOS flip-flop.

Ⅲ Bistable flip-flop

Bistable flip-flop basic circuit

The basic circuit is shown in the upper half of the Figure. It is formed by directly coupling two inverters. Inverter 1 is composed of transistor T1 and resistors Rc1, R11, and R12, and inverter 2 is composed of transistor T2 and resistors Rc2, R21, and R22. The output terminal Q of inverter 1 is the input terminal of inverter 2. Similarly, the output terminal Q of inverter 2 is also the input terminal of inverter 1, and the two-stage inverters feedback to each other. This circuit has two stable states:

One steady state is that the T1 tube is on, the T2 tube is off, the Q terminal is low potential, and the Q’  terminal is high potential; the other steady-state is that the T1 tube is off and the T2 tube is on, the Q terminal is a high potential, and the Q’  terminal is low potential. After adding the voltages Ec and -Eb, the circuit enters a stable state. If no trigger signal is added, the circuit will always be in this stable state.

To switch the circuit from one steady-state to another, a trigger signal must be added. The lower part of the Figure is the two circuits that lead the trigger signal to each inverter. They are composed of differential circuits R1C1, R2C2, and isolation diodes D1, D2.

When an external negative trigger pulse acts on the "S" end of the pilot circuit, D1 is turned on through the differential circuit R1C1, and the b1 point is a low potential. At this time, no matter what state the trigger is in, the T1 tube is turned off, the Q point becomes a high potential, the T2 tube is turned on, and the tee point becomes a low potential. This steady state is called the "set" state of the flip-flop, and the "S" terminal is called the "set" terminal. Conversely, when a negative trigger pulse is applied to the "R" terminal, the R terminal will be at a high potential and the Q terminal will be at a low potential. This steady-state is the "reset" state of the flip-flop, and the "R" end is called the "reset" end. Flip-flops with set and reset functions are called R-S flip-flops. Bistable flip-flops can be used to form various counters, frequency dividers, and registers.

Ⅳ Emitter coupling flip-flop

Emitter coupling flip-flop

It is also known as a Schmitt trigger, its principle circuit is shown in Figure. It is also directly coupled by two-stage inverters. The output terminal c1 of the first stage inverter is the input terminal of the second stage inverter. The input terminal of the first stage inverter is connected to the input trigger voltage ui, and the output terminal of the second stage inverter provides the output voltage u0. The two-stage inverters are coupled together through a common emitter resistance Re, so they are called emitter coupling flip-flops. This kind of flip-flop also has two stable states, one steady state is that the T1 tube is on, the T2 tube is off, and the output u0 is high; the other is that the T1 tube is off, the T2 tube is on, and u0 is a low potential. The stable state of the flip-flop is determined by the level of the input u potential, so this flip-flop has potential trigger characteristics. When the input ui is at a low potential, the T1 tube is cut off, the potential at point c1 rises, and the T2 tube is turned on, and the output u0 is also a low potential. When ui is a high potential, the T1 tube is turned on, and the potential at point c1 drops, so that the T2 tube is cut off, and u is also a high potential. The emitter coupling trigger can be used for waveform shaping and amplitude discrimination.

Ⅴ Monostable flip-flop

Monostable flip-flop and voltage waveform

The monostable flip-flop also consists of two inverters. Compared with the bistable flip-flop, inverter 2 composed of the transistor T2 is completely the same. But in inverter 1 composed of the transistor T1, the capacitor C is used instead of the resistor R11, and R12 is connected to Ec. In addition, a pilot circuit composed of D1, R1, and C1 is connected to point b1 of the T1 tube, and ui is an external trigger signal. The state voltage of the flip-flop is output from points c1 and c2.

The waveform in the Figure shows the working process of the monostable flip-flop. Before the arrival of the negative flip-flop pulse u (from 0 to t1), the flip-flop is in a stable state. Since point b1 is connected to voltage Ec through R12, T1 turns on and T2 turns off. The voltage uc1 at point c1 is a low potential, and the voltage u at point c2 is a high potential, and the capacitor C is charged. At the instant t=t1, u arrives, D1 is turned on through the differential circuit R1C1, b1 is low, T1 changes from on to off, uc1 rises to high potential; T2 turns on, uc2 drops to low potential. At this time, the capacitor C discharges through T2 to form a temporary stable state (a period from t1 to t2), which is called a transient stable state. With the discharge of capacitor C, the potential at point b1 rises. When t=t2, the potential at point b1 turns on the T1 tube, uc1 drops to a low potential and the T2 tube turns off, and the uc2 potential rises. During t2 to t3, uc2 rises slowly due to the influence of Rc2C charging, forming a recovery period. After t3, it enters the original stable state. The monostable flip-flop can be used for pulse shaping and pulse delay.

Various flip-flops can be composed of discrete components, and can also be implemented by integrated circuits. However, with the development of integrated circuit technology, the variety of integrated flip-flops has gradually increased, with excellent performance and increasingly widespread applications.

Ⅵ The relationship between flip-flops and latches

The circuit diagram of the flip-flop is composed of logic gates, and its structure is derived from the R-S latch (a flip-flop in a broad sense includes a latch). The flip-flop can handle the interaction between the input and output signals and the clock frequency.

Flip-flops and latches

A D flip-flop is formed by adding an additional circuit composed of two AND gates and one NOT gate in front of the R-S latch. When the clock pulse CP is 1, the data from the input terminal D is read in and transmitted to the output terminal; when the CP is 0, according to the characteristic of the AND gate that "as long as one input terminal is 0, the output is 0", the input terminal D The data is shielded by the AND gate and cannot reach the output terminal. No matter how the input D changes, the output value of the Q terminal remains unchanged. Only when the next CP high level comes will the current D value be sent out. In this way, the function of delayed output that is temporarily saved is realized. It can be seen from the action of the circuit that the clock input plays a control role. When CP is 1, it can trigger the subsequent latch to temporarily latch the value of D. The flip-flop uses the storage principle of the latch, but the flip-flop function is added to control the storage time.