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In recent years, IC packaging technologies have emerged and new terms have emerged. There are at least a few dozen IC packaging-related names that can be listed.
We divide IC packaging into two major categories: (i) IC packaging technologies based on XY plane extension, which mainly extend and interconnect signals through RDL; and (ii) IC packaging technologies based on Z-axis extension, which mainly extend and interconnect signals through TSV.
The XY plane here refers to the XY plane of the wafer or chip. The distinctive feature of this type of package is that there are no TSV silicon vias, and its signal extension means or technology is mainly realized through RDL layers, usually without a substrate. The RDL wiring is attached to the silicon body of the chip or to an additional Molding. Because the final package has no substrate, these packages are relatively thin and are now widely used in smartphones.
FOWLP (Fan-out Wafer Level Package) is a kind of WLP (Wafer Level Package), so we need to understand WLP wafer-level package first.
Before the emergence of WLP technology, the traditional packaging process was mainly carried out after the dicing of bare wafers, where the wafers were first diced and then packaged into various forms.
WLP was introduced around 2000, and there are two types: Fan-in and Fan-out.
After the packaging is completed, the wafer is cut and sliced. The size of the packaged chip is almost the same as the bare chip, so it is also called CSP (Chip Scale Package) or WLCSP (Wafer Level Chip Scale Packaging). These packages are in line with the market trend of light, small, short, and thin consumer electronics.
In the beginning, WLPs were mostly in Fan-in form, which can be called Fan-in WLP or FIWLP, and were mainly used for chips with small areas and low pin counts.
With the improvement of the IC process, the chip area shrinks, and the chip area cannot accommodate a sufficient number of pins. Therefore, the Fan-Out WLP package form, also known as FOWLP, was developed to make full use of RDL outside the chip area to make connections for more pins.
The flow of the FOWLP package is shown in the figure below.
FOWLP Packaging Process
InFO (Integrated Fan-out) is a FOWLP IC packaging technology developed by TSMC in 2017. It is an integration on the FOWLP process, which can be understood as the integration of multiple chips Fan-Out process, while FOWLP favors the Fan-Out package process itself.
InFO gives room for multiple chip integration and can be applied to RF and wireless chip packaging, processor and baseband chip packaging, and graphics processor and network chip packaging. The following diagram shows the comparison of FIWLP, FOWLP, and InFO.
FIWLP, FOWLP and InFO comparison schematic
Apple iPhone processors have been produced by Samsung in the early years, but TSMC from Apple A11 began to take two generations of iPhone processor orders. One of the keys lies in TSMC's new packaging technology InFO, which allows direct interconnection between chips, reducing the thickness and freeing up valuable space for batteries or other parts.
Apple started InFO packaging from the iPhone 7 and continues to use it subsequently. iPhone 8 and iPhone X, including other brands of cell phones in the future, will also start using this technology generally. The addition of Apple and TSMC has changed the application status of FOWLP technology and will enable the market to begin to gradually accept and commonly apply FOWLP (InFO) packaging technology.
FOPLP (Fan-out Panel Level Package) is based on the idea and technology of FOWLP but uses a larger panel, so it can be mass-produced in a package several times larger than a 300 mm silicon wafer chip.
FOPLP technology is an extension of FOWLP technology, which is a Fan-Out process on a larger square carrier board, hence the name FOPLP packaging technology.
Currently, FOPLP uses a 24×18-inch (610×457mm) PCB carrier board, which is about four times the area of a 300 mm silicon wafer. Therefore, it can be simply considered that in a single process, it is possible to mass-produce 4 times more IC packages than 300 mm silicon wafers.
Like the FOWLP process, the FOPLP technology can integrate the front and backstages of the packaging process and can be considered as a single package process, thus significantly reducing production and material costs. The figure below shows the comparison between FOWLP and FOPLP.
Comparison of FOWLP and FOPLP
FOPLP adopts the production technology on PCB for RDL production, its line width and line pitch are currently greater than 10um, and SMT equipment is used for chip and passive device placement. Since its panel area is much larger than the wafer area, it can package more products at one time. Compared with FOWLP, FOPLP has greater cost advantages. At present, the world's major packaging companies, including Samsung Electronics and Sun and Moon, are actively involved in FOPLP process technology.
EMIB (Embedded Multi-Die Interconnect Bridge) embedded multi-chip interconnect bridge IC packaging technology is proposed by Intel and actively applied. Different from the three types of IC packages described earlier, EMIB is a substrate class package. Because EMIB also does not have TSV, it is also classified as an IC packaging technology based on XY plane extension.
The EMIB concept is similar to the 2.5D package based on the silicon intermediate layer, which is a localized high-density interconnection through the silicon wafer. Compared to the traditional 2.5 packages, EMIB technology has the advantages of normal package yield, no additional process, and simple design because there is no TSV.
With traditional SoC chips, the CPU, GPU, memory controller, and IO controller can all be manufactured using only one process. With EMIB technology, the CPU and GPU can use 10nm process, the IO unit and communication unit can use 14nm process, and the memory part can use 22nm process. Using EMIBIC packaging technology, the three different processes can be integrated into one processor. The diagram below shows the EMIB diagram.
EMIB
Compared with the silicon interposer, EMIB silicon area is smaller and more flexible. EMIB packaging technology can package CPU, IO, GPU, and even FPGA, AI, and other chips together as needed. And it can package chips of 10nm, 14nm, 22nm, and other different processes together into a single chip to adapt to the needs of the flexible business.
Through the EMIB approach, the KBL-G platform integrates Intel Core processors with AMD Radeon RX Vega M GPUs, providing both the powerful computing capabilities of Intel processors and the outstanding graphics capabilities of AMD GPUs. This chip makes history and brings the product experience to a new level.
Z-axis extension-based IC packaging technology is mainly used for signal extension and interconnection through TSV, which can be divided into 2.5D TSV and 3D TSV, through which multiple chips can be vertically stacked and interconnected.
In 3D TSV technology, the chips are close to each other, so there will be less delay. In addition, the shorter interconnect length reduces the associated parasitic effects and allows the device to operate at a higher frequency, which translates into improved performance and greater cost reduction.
TSV technology is a key technology for 3D packaging, and research organizations including semiconductor integration manufacturers, IC manufacturing foundries, packaging foundries, emerging technology developers, universities and research institutes, and technology consortia have developed multiple aspects of the TSV process.
Although Z-axis extension-based IC packaging technology is mainly used for signal extension and interconnection via TSV, RDL is also indispensable, for example, if the TSVs of the upper and lower layers of the chip cannot be aligned, local interconnection via RDL is required.
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's 2.5D packaging technology that packages the chip onto a silicon interposer (intermediate layer) and interconnects it using high-density wiring on the silicon interposer before mounting it on the package substrate, as shown in the figure below.
CoWoS
CoWoS and InFO are both from TSMC, CoWoS has Silicon Interposer and InFO does not. CoWoS is for the high-end market, the number of wires and the package size are larger. InFO is for cost-effective market, the package size is smaller and the number of wires is smaller.
TSMC started mass production of CoWoS in 2012, packaging multiple chips together through this technology. Through Silicon Interposer high-density interconnect, it achieves a small package size, high performance, low power consumption and fewer pins.
CoWoS technology is widely used, Nvidia's GP100, the Google chip TPU2.0 behind AlphaGo that defeated Ke Jie are all using CoWoS technology. Artificial intelligence AI is also behind the contribution of CoWoS. Currently, CoWoS is supported by high-end chip manufacturers such as NVIDIA, AMD, Google, XilinX, and Huawei.
HBM (High-Bandwidth Memory) is a high-bandwidth memory targeted at the high-end graphics market. HBM uses 3D TSV and 2.5D TSV technologies to stack multiple memory chips together in 3D TSV, and 2.5D TSV technology to interconnect the stacked memory chips with the GPU on the carrier board. The diagram below shows a schematic of HBM technology.
HBM（High-Bandwidth Memory ）
HBM is currently available in three versions, HBM, HBM2, and HBM2E, with bandwidths of 128 GBps/Stack, 256 GBps/Stack, and 307 Gbps/Stack respectively, with the latest HBM3 still under development.
AMD, NVIDIA, and Hynix are pushing the HBM standard, with AMD first using it for its flagship graphics cards, with memory bandwidths of up to 512 Gbps, and NVIDIA following suit, using HBM to achieve 1TBps of memory bandwidth. Compared to DDR5, HBM improves performance by more than 3 times but reduces power consumption by 50%.
HMC (Hybrid Memory Cube) is a hybrid storage cube whose standard is being pushed by Micron. Its target market is the high-end server market, especially for multi-processor architectures. HMC uses stacked DRAM chips to achieve greater memory bandwidth. In addition, HMC integrates the Memory Controller into the DRAM stacked package through 3D TSV integration technology. The diagram below shows the HMC technology.
HMC
The difference between HBM and HMC is that HBM is interconnected with the GPU through the Interposer, while HMC is mounted directly on the Substrate, missing the Interposer and 2.5D TSV.
In the HMC stack, the 3D TSVs are about 5~6um in diameter and number more than 2000+. DRAM chips are usually thinned to 50um and the chips are connected to each other through a 20um MicroBump.
In the past, memory controllers were made in the processor, so in high-end servers, when a large number of memory modules are needed, the design of memory controllers is very complicated. Now that the memory controller is integrated into the memory module, the design of the memory controller is greatly simplified. In addition, HMC uses a high-speed serial interface (SerDes) to implement a high-speed interface, which is suitable for situations where the processor and memory are far apart.
Wide-IO (Wide Input Output) is a technology promoted by Samsung and is now in its second generation, enabling memory interface bit widths of up to 512 bits, memory interface operating frequencies of up to 1GHz, and total memory bandwidths of up to 68GBps, twice the bandwidth of DDR4 interfaces (34GBps).
Wide-IO is implemented by stacking Memory chips on Logic chips, and Memory chips are connected to Logic chips and substrate through 3D TSV as shown in the figure below.
Wide-IO
With the advantage of the vertical stacking package of TSV architecture, Wide-IO helps to create mobile memory with speed, capacity, and power characteristics to meet the needs of mobile devices such as smartphones, tablets, and handheld game consoles. Its main target market is mobile devices requiring low power consumption.
In addition to the EMIBIC package introduced earlier, Intel has also introduced Foveros active on-board technology. In Intel's technology introduction, Foveros is called 3D Face to Face Chip Stack for heterogeneous integration, a three-dimensional face-to-face heterogeneous integration chip stack.
The difference between EMIB and Foveros is that the former is a 2D packaging technology, while the latter is a 3D stacking packaging technology. Compared to the 2D EMIB packaging method, Foveros is more suitable for small form factor products or products with higher memory bandwidth requirements. In fact, the differences between EMIB and Foveros in terms of chip performance and functionality are not significant, as both are chips with different specifications and functions integrated together to play different roles. However, in terms of volume, power consumption, etc., the advantages of Foveros 3D stacking emerge.
The following figure shows the schematic of Foveros 3D packaging technology.
Foveros
Co-EMIB is a combination of EMIB and Foveros. EMIB is mainly responsible for the horizontal linkage, allowing chips with different cores to be put together like a puzzle. Foveros, on the other hand, is a vertical stack, like building a tall building, where each floor can have a completely different design, such as a gym on the second floor, an office building on the second floor, and an apartment on the third floor.
The packaging technology that combines EMIB and Foveros is called Co-EMIB and is a chip fabrication method that can have higher flexibility, allowing the chips to continue to be stitched horizontally while stacking. Thus, this technology allows multiple 3D Foveros chips to be stitched together via EMIB to create larger chip systems. The diagram below shows the schematic of Co-EMIB technology.
Co-EMIB（Foveros + EMIB）
Co-EMIB packaging technology can provide performance comparable to that of a single chip. The key to achieving this technology is ODI (Omni-Directional Interconnect), which has two different types of connections, not only elevator-type connections to different layers but also bridges to different three-dimensional structures and mezzanine layers between layers, allowing different chip combinations to have high flexibility. ODI packaging technology allows both horizontal and vertical interconnection of chips.
Co-EMIB, through a new 3D + 2D packaging approach, also turns chip design thinking from the flat puzzle of the past to stacking blocks. Therefore, in addition to revolutionary new computing architectures such as quantum computing, CO-EMIB is the best way to maintain and continue the existing computing architecture and ecology.
SoIC, also known as TSMC-SoIC, is a new technology proposed by TSMC - System-on-Integrated-Chips (SoIC).
SoIC is an innovative multi-chip stack technology that enables wafer-level integration of sub-10nm processes. The most distinctive feature of this technology is the no-Bump bonding structure, which results in higher integration density and better operational performance.
SoIC contains two types of technology forms, CoW (Chip-on-wafer) and WoW (Wafer-on-wafer), from TSMC's description, SoIC is a WoW wafer-to-wafer or CoW chip-to-wafer direct bonding (Bonding) technology, which belongs to the Front-End 3D technology (FE 3D), while the aforementioned InFO and CoWoS are the most important technologies. TSMC and Siemens EDA (Mentor) have collaborated on SoIC technology and introduced related design and verification tools.
The figure below shows a comparison of 3D IC and SoIC integration.
Comparison of 3D IC and SoIC integration
Specifically, the process of SoIC and 3D IC is somewhat similar. The key of SoIC lies in achieving a bump-free bonding structure and its TSV density is also higher than that of traditional 3D IC, which directly interconnects multiple layers of chips through very tiny TSVs. The figure above shows the comparison of TSV density and Bump size between 3D ICs and SoICs. It can be seen that the TSV density of SoIC is much higher than that of 3D IC, and the interconnection between chips is also made by no-Bump direct bonding technology, which results in smaller chip pitch and higher integration density, and thus its products have higher functional density than traditional 3D IC.
X-Cube (eXtended-Cube) is a 3D integration technology announced by Samsung to fit more memory in a smaller space and reduce the signal distance between cells.
X-Cube is used in processes that require high performance and bandwidth, such as 5G, artificial intelligence, and wearable or mobile devices, as well as in applications that require high computing power. x-Cube utilizes TSV technology to stack SRAM on top of the logic cell, allowing more memory to fit in a smaller space.
X-Cube
As seen in the X-Cube technology demonstration diagram, unlike previous 2D parallel packages of multiple chips, the X-Cube 3D package allows multiple chips to be stacked and packaged, resulting in a more compact finished chip structure. The TSV technology is used to connect the chips to each other, reducing power consumption while increasing the transmission rate. This technology will be used in cutting-edge 5G, AI, AR, HPC, mobile chips, and VR.
X-Cube technology dramatically shortens the signal transmission distance between chips, increases data transmission speed, reduces power consumption, and also allows for customization of memory bandwidth and density according to customer needs. Currently, X-Cube technology can already support 7nm and 5nm processes, and Samsung will continue to work with global semiconductor companies to deploy the technology in the next generation of high-performance chips.
In this article, we have described 12 of the most mainstream IC advanced packaging technologies available today. The following table is a side-by-side comparison of these mainstream IC packaging technologies.
Horizontal comparison of mainstream advanced packaging technologies
From the comparison, we can see that the emergence and rapid development of advanced packaging are mainly in the past 10 years, its integration technology mainly includes 2D, 2.5D, 3D, 3D+2D, 3D+2.5D several types, functional density is also low, medium, high, very high several, application areas include 5G, AI, wearable devices, mobile devices, high-performance servers, high-performance computing, high-performance graphics cards The main application manufacturers include TSMC, Intel, SAMSUNG and other famous chip manufacturers, which also reflects the trend of integration of IC packaging and chip manufacturing.
Finally, let's summarize: the purpose of advanced packaging is to:
Improve functional density, shorten interconnect length, improve system performance, and reduce overall power consumption.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 