PLL (Phase Locked Loop): It is a phase-locked loop or a phase-locked loop, which is used to unify and integrate clock signals to make high-frequency devices work normally, such as memory access data. PLL is used for feedback technology in oscillators. For many electronic devices to work normally, the external input signal is usually synchronized with the internal oscillating signal. Ordinary crystal oscillators cannot achieve very high frequencies due to process and cost reasons. When high frequency applications are required, the corresponding device VCO can be converted to high frequency, but it is not stable, so the phase-locked loop can be used. Realize a stable and high-frequency clock signal.

Ⅰ. What is PLL(Phase Locked Loop)?

PLL (Phase Locked Loop): A phase-locked loop (PLL) unifies the integration of clock signals to allow high-frequency devices, such as memory access data, to function normally. In oscillators, PLL is utilized for feedback technology. The external input signal is frequently synced with the internal oscillating signal for many electrical gadgets to function normally. Due to technological and cost constraints, ordinary crystal oscillators are unable to produce very high frequencies. When high-frequency applications are needed, the coresponding device VCO can be changed to high frequency, but it is not stable, thus the phase-locked loop can be utilized instead. Create a clock signal that is both stable and high-frequency.

Ⅱ. What’s the Structure of PLL?

A phase-locked loop is a feedback control circuit that is also known as a phase-locked circuit (PLL, Phase-Locked Loop). The phase-locked loop has the property that the reference signal input from the outside controls the frequency and phase of the oscillating signal inside the loop. The phase-locked loop is commonly employed in closed-loop tracking circuits because it can automatically track the frequency of the output signal to the frequency of the input signal. When the frequency of the output signal equals the frequency of the input signal, th output voltage and the input voltage retains a fixed phase difference, which is phase lock, during the operation of the phase-locked loop. The story behind the ring's name. PD, Phase Detector, LF, Loop Filter, and VCO, Voltage Controlled Oscillator, and feedback circuit are the four sections of a phase-locked loop.

The job of a phase comparator, also known as a phase detector, is to detect the phase difference between input and output signals and transform the discovered phase difference signal into an uD(t) voltage signal output. The control voltage uC(t) of the voltage-controlled oscillator is created after filtering by the low-pass filter, and the frequency of the oscillator's output signal is controlled.

Loop Filter: Filter the phase comparator's output to remove the signal from the voltage-controlled oscillator (VCO) circuit, and increase the phase-locked loop's stability by removing the high-frequency and DC components from the phase difference signal stream;

Voltage Controlled Oscillator (VCO): The output radio frequency signal is generated under the control of the phase difference signal output by the phase comparator/phase detector.

Feedback path: A frequency divider may be used to separate the loop's operational frequency band from the frequency of the phase detector's output signal.

The phase-locked loop's basic block diagram is depicted in Figure.

Ⅲ. How many types of PLL?

Analog phase-locked loop (PLL/APLL)

A first-order phase-locked loop with a loop filter frequency response equal to that of a single-pole low-pass filter and a more flexible and complicated second-order phase-locked loop is utilized in communication applications.

Digital Phase Locked Loop (DPLL/ADPLL)

Ordinary DPLLs, which utilize digital phase detectors, analog VCOs, and loop filters, and all-digital phase-locked loops (ADPLLs), which use all digital components, are used for non-communication applications.

Software Phase Locked Loop (SPLL/ASPLL)

SPLL is mostly used for data and clock recovery. It has more flexibility because most of it can be accomplished with software.

Neuron Phase Locked Loop (NPLL)

In brain biomedical modeling, NPLL uses an artificial neural network (ANN) as part of the feedback loop for automatic voice recognition and time coding.

Ⅳ. How does PLL Work?

The phase-locked loop is a type of feedback circuit that synchronizes the phase of the circuit's clock with that of an external clock. The phase of the external signal is compared to the phase of the voltage-controlled crystal oscillator in the PLL to ensure synchronization (VCXO). During the comparison, the phase-locked loop circuit will alter the clock phase of the local crystal oscillator based on the phase of the external signal until two of them are equal. The signal's phase is synced. The phase-locked loop is a particularly valuable synchronization mechanism in the data acquisition system since it allows separate data acquisition boards to share the same sampling clock. As a result, the phases of all boards' local 80MHz and 20MHz clocks are synced, and the sampling clock is synchronized as well. Data may be captured precisely at the same moment because each board's sample clock is synced.

Depending on the hardware board you're using, the programming techniques necessary to synchronize the sample clocks of various boards via a phase-locked loop will differ. All synchronization is performed using the clock and trigger lines on the RTSI bus for devices based on the PCI bus (M series data acquisition cards, PCI digitizers, and so on); at this time, one of the boards will operate as the primary card and output its internal clock. Other slave boards can acquire this clock signal for synchronization via the RTSI channel. It is accomplished for products based on the PXI bus by synchronizing the clocks of all boards with the PXI bus's built-in 10MHz backplane clock. The PLL has been synced.

A frequency reference, phase detector, charge pump, loop filter, and voltage-controlled oscillator make up a simple PLL (VCO). Two frequency dividers will be added to the frequency synthesizer based on PLL technology: one to lower the reference frequency and the other to divide the VCO. Furthermore, combining the phase detector and the charge pump into a single functional block for analysis is simple. The addition of these digital frequency divider circuits to the traditional PLL allows for easy frequency modification. The processor will simply "write" a new frequency division value into a PLL register, update the VCO's operating frequency, and so alter the wireless device's operational channel.

PLL is a closed-loop control system that compares the phase of the reference signal to the phase of the VCO. The frequency synthesizer with the added reference and feedback divider is in charge of adjusting the phase by comparing the two set values of the divider. In most systems, the phase comparison is done in the phase detector, which is a phase and frequency detector. Within a phase error range of 2, the phase-frequency detector generates an error voltage that is essentially linear and remains constant when the error is bigger than 2. The phase-frequency comparator's dual-mode operation allows it to create a faster PLL lock time for big frequency mistakes (for example, when the PLL is initiated during power-up) while avoiding harmonic locking.

The tuning voltage is used by the VCO to generate a frequency. The VCO might be a module, an integrated circuit, or a collection of discrete components. Inside the MAX2361 transmitter, IC is a VCO constructed with active components. Design engineers can set IF (Intermediate Frequency) LO (Local Oscillator) to enable certain radio frequency schemes because the resonant tank and varactor diodes are external.

--- The loop filter combines the current pulses generated by the phase-frequency detector's charge pump to generate a tuning voltage for the VCO. To make the phase of the VCO lead and increase the frequency of the VCO, the typical way is to increase the tuning voltage from the loop filter (to a greater positive value). An operational amplifier or passive components such as resistors and capacitors can be utilized to implement the loop filter. The PLL bandwidth is determined by the loop filter's time constant, as well as the gains of the VCO, phase detector, and divider. The transient response, reference spurious level, and noise filtering properties are all determined by the PLL bandwidth. The phase noise on the frequency synthesizer's output is primarily obtained from the phase noise of the phase detector inside the PLL bandwidth; beyond the PLL bandwidth, the output phase noise is primarily produced from the VCO phase noise.

--- The frequency synthesizer is a device that synthesizes frequencies. The PLL reference input is a constant frequency signal that is stable and devoid of interference. Most radio equipment uses a crystal oscillator because its phase noise is relatively low and its frequency is stable and finely regulated. The PLL divides the reference frequency to provide the phase-frequency detector a lower frequency. By increasing the feedback divider setting value by "1," the lower frequency will set the detector's comparison rate and establish the smallest possible frequency step. This determines the synthesizer's frequency resolution (i.e., frequency step size), which should be equal to or less than the radio system's channel spacing. The phase detector and loop filter generate a tuning voltage using the VCO output scaled down by the feedback divider.

Input signal -> phase detector -> low pass filter -> voltage controlled oscillator -> output signal. The input signal and the output signal of the voltage regulated oscillator are both fed into the phase detector. When the phase and frequency differences between the two input signals are small, the phase detector's output is proportional to the difference between them. The phase detector produces an analog signal, which is then passed through a low-pass filter to remove high-frequency clutter before entering the voltage-controlled oscillator. The voltage-controlled oscillator's output frequency changes as the input voltage changes. PLL is a negative feedback system in which the output signal may keep up with the input signal for "a set period of time" as long as the input signal is within the usual range. The process of the output signal tracking the input signal after the input signal changes is known as capture; when the output signal is tracked, it is known as a lock; when the input signal changes too quickly and the output signal cannot be tracked, it is known as loss of lock. PLL can easily achieve N frequency multiplication, and the principle is as follows:

Input signal -> Phase detector -> Low pass filter -> Voltage controlled oscillator -> Output signal

^|______N Divider______________|

In addition, fractional frequency multiplication can be realized, and the principle is as follows:

Input signal -> Phase detector -> Low pass filter -> Voltage controlled oscillator -> Output signal

^|________N divider/N+1 divide_________|

| |

|------ Mode control ――---------> |

If the mode control module realizes the divider, it can pick whether the divider is in the N divider or the N+1 divider.

If 9 CLK is divided by N and 1 CLK is divided by N+1, the actual output signal frequency is (N+0.1).

Because the PLL circuit is essentially an analog circuit that is distinct from the digital circuit of the ARM core, it exists in its own state within the CPU.

Furthermore, many CPUs' PLL power supply is a distinct power source, and the PLL power supply's quality is relatively good.

Ⅴ. Where to use PLL?

Phase-locked loops are employed in a variety of radiofrequency applications and are required components for radio receivers, test equipment, demodulators, and frequency synthesizers, among others.

[1] Application of phase-locked loop in modulation and demodulation

(1) The concept of modulation and demodulation

The signal is usually modulated by the modulation method at the broadcasting end in order to realize long-distance transmission of information, and the signal must be demodulated after the receiving end gets the signal to restore the original signal.

The term "modulation" refers to the use of the information-carrying input signal ui to alter the parameters of the carrier signal uc, such that a specific parameter of the carrier signal varies when the input signal changes. The carrier signal has three parameters: amplitude, frequency, and phase. As a result, amplitude modulation (AM), frequency modulation (FM), and phase modulation are the three types of modulation (PM).

The frequency of the amplitude modulation wave is equal to the frequency of the carrier signal, and the amplitude changes with the amplitude of the input signal; the frequency of the frequency modulation wave is equal to the frequency of the carrier signal, and the amplitude changes with the amplitude of the input signal; The amplitude is equal to the carrier signal's amplitude, while the phase changes with the input signal's amplitude. The picture depicts schematic schematics of the AM and FM waves.

The input signal, also known as the modulation signal, is shown in figure (a); the carrier signal is shown in figure (b), and the amplitude modulation wave and frequency modulation wave signal are shown in figure (c).

Demodulation is the inverse of modulation, allowing the modulated wave uo to be restored to the original signal ui.

[2] In frequency modulation and demodulation circuits, phase-locked loops are used.

The FM wave has the property that the frequency changes with the modulation signal's amplitude. The oscillation frequency of the voltage-controlled oscillator is dependent on the amplitude of the input voltage, as shown by formula 3. When the carrier signal's frequency is identical to the phase-locked loop's natural oscillation frequency 0, the voltage-controlled oscillator's output signal's frequency remains 0 unchanged. The frequency of the voltage-controlled oscillator's output signal is centered on 0, which changes with the amplitude of the modulation signal and the changing FM wave signal if the input signal of the voltage-controlled oscillator includes a modulation signal ui in addition to the signal uc output by the phase-locked loop low-pass filter. The frequency modulation circuit can be made up of a phase-locked loop, as can be seen. The illustration depicts a block diagram of a frequency-modulation circuit made up of a phase-locked loop.

The block diagram of the demodulation circuit is illustrated in Figure 3, and it is based on the phase-locked loop's working principle and the properties of the FM wave.

If an FM signal is used, the loop's passband should be large enough for the signal modulation spectrum to fit inside the bandwidth. Figure 6.1 shows how the frequency of the voltage-controlled oscillator reflects the change in input modulation at this point. Please refer to the literature on phase-locked technology for a full analysis of phase-locked loops. This document just explains the idea of phase-locked loop frequency discrimination. It is simple to assume that the tracking error between the voltage-controlled oscillator's frequency and the frequency of the input signal can be ignored. As a result, the voltage-controlled oscillator's frequency v(t) is always equal to the FM wave's instantaneous frequency FM(t).

[3] Application of phase-locked loop in frequency synthesis circuit

A quartz crystal oscillator is commonly employed in current electronic technology to generate a high-precision oscillation frequency. The quartz crystal oscillator's frequency, on the other hand, is difficult to adjust. A multi-frequency, extremely stable oscillation signal output can be created using a phase-locked loop, frequency multiplication, frequency division, and other frequency synthesis techniques.

A phase-locked frequency multiplier circuit has an output signal frequency greater than the crystal oscillator signal frequency, whereas a phase-locked frequency divider circuit has an output signal frequency lower than the crystal oscillator signal frequency. The graphic depicts a block diagram of the phase-locked frequency multiplication and phase-locked frequency division circuit.

When N in the figure is more than 1, it is a frequency divider circuit; when N is less than 1, it is a frequency multiplier circuit.

Ⅵ. What are the Characteristic Parameters of PLL?

Time to lock

The time it takes for the output signal to approach and stabilize the input reference signal is a critical reference indicator. The less time it takes to reach the locked state, the less time it takes to synchronize communication, and the less synchronization code is necessary. It's possible to use it to send additional data.

The gain setting in the filter, the starting static frequency of the VCO, and other factors all have an impact on the lock time.

This is the same PLL as before. When the signal to be generated and the initial static frequency deviation change, the time it takes to reach steady-state differs as well. When the input reference frequency and the static starting frequency are significantly different, the time to attain steady-state increases dramatically. The longer it is, the better.

Steady-state error

There will be a steady-state inaccuracy in the PLL even if it has finished locking. The steady-state error is determined by the loop filter type and the input signal type. In general, the higher the loop filter's order, the more signals can be locked, as illustrated in the diagram below.

The following are the three categories of input signals:

The phase is changed, and there is a step function change in the phase error.

Although the frequency varies, the rate of change in the phase error remains constant.

The frequency varies and changes, and the pace of mistake change is also increasing.

PLLs of different orders have different locking capacities, as can be observed. The greater the order, the better the PLL's locking capabilities. A 2nd order PLL can perform a wide range of synchronization tasks.

Capabilities for tracking and transient behavior

Three elements influence transitory behavior and tracking ability:

The type of PLL impacts whether the output can be stable and whether steady-state errors will occur, among other things.

The PLL's bandwidth determines how long it takes to establish a lock. The lower the bandwidth, the longer it takes to acquire the lock.

The PLL damping coefficient, which influences overshoot and speed, is usually 1/√(2) or 1.

Bandwidth

The bandwidth refers to the frequency range in which the PLL functions, as well as the frequency range in which the PLL's noise occurs.

The wider the PLL's bandwidth, the wider the frequency range that can be locked; however, the wider the bandwidth, the more noise that can enter the PLL, resulting in poor signal quality.

The lower the PLL's bandwidth, the longer it takes to lock, but the signal quality is improved, and the floating range above and below the required frequency is reduced.