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CPLD (Complex Programmable Logic Device) is mainly composed of programmable logic macrocells (MC) around the center of the programmable interconnect matrix cell. Among them, the MC structure is more complex and has a complex I/O cell interconnection structure, which can be generated by the user according to the needs of a specific circuit structure to complete certain functions. Since the CPLD uses fixed-length metal wires for the interconnection of each logic block internally, the designed logic circuits are time-predictable, avoiding the disadvantage that the timing of segmented interconnection structure is not completely predictable.
In the 1970s, the earliest programmable logic device, the PLD, was born. Its output structure was programmable logic macrocells. Because its hardware structure design could be done by software, its design was highly flexible than that of pure hardware digital circuits. But its overly simple structure also made them capable of implementing only small-scale circuits. To make up for this shortcoming that PLDs can only design small-scale circuits, complex programmable logic devices - CPLDs - were introduced in the mid-1980s.
CPLD has the features of flexible programming, high integration, short design and development cycle, wide applicability, advanced development tools, low design and manufacturing cost, low hardware experience requirement for designers, no testing required for standard products, high confidentiality, and popular price, etc. It can realize larger scale circuit design, so it is widely used in product prototyping and product production (generally below 10,000 pieces). CPLD devices have become an indispensable part of electronic products, and their design and application have become a necessary skill for electronic engineers.
CPLD is a kind of digital integrated circuit that users construct their own logic functions according to their needs. The basic design method is to use the integrated development software platform to generate the corresponding target file by using schematic diagram and hardware description language and then transfer the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system.
Here is the design (decoration) process of the snatcher as an example, i.e. the design flow of the chip. most of the work of the CPLD is done on the computer. Open the integrated development software (Altera Max+pluxII) → draw a schematic diagram, write hardware description language (VHDL, Verilog) → compile → give the input excitation signal of the logic circuit, simulate, and check whether the logic output result is correct → carry-out pin input and output locking (64 input and output pins of 7128 can be set as needed) → generate code → transfer and store the code in the CPLD chip through the download cable.
7128 chip pins have been introduced. The digital tube, quiz switch, indicator, buzzer through the wire to the chipboard
System interface circuit using CPLD chip and then power on the test. When the quiz switch is pressed, the indicator light of the corresponding bit should be on. After the answer is correct, the referee will add points to see if the digital display is correct at this time. If you find any problem, you can modify the schematic diagram or hardware description language again to improve the design. After the design, such as mass production, you can directly copy other CPLD chips, that is, write the code can be. If you want to do other designs on the chip, such as traffic light design, you have to draw the schematic diagram or write the hardware description language again, and repeat the above work process to complete the design. This modification of the design is equivalent to redecorating the house, and this renovation can be performed tens of thousands of times for CPLDs.
System interface circuit using CPLD chip
After decades of development, many companies have developed CPLD programmable logic devices. The more typical ones are the products of Altera, Lattice, and Xilinx, the world's three most authoritative companies. The commonly used chips are given here:
Altera EPM7128S (PLCC84)
Lattice LC4128V (TQFP100)
Xilinx XC95108 (PLCC84)
A CPLD consists of three main components: a logic block, a programmable interconnect channel, and an I/O block.
The logic block in CPLD is similar to a small-scale PLD. Usually, a logic block contains 4 to 20 macrocells, each of which is generally composed of a product term array, product term assignment, and programmable registers. Each macrocell has multiple configurations, and each macrocell can be used in cascade, so that more complex combinational logic and timing logic functions can be realized. For highly integrated CPLDs, embedded array blocks with on-chip RAM/ROM are usually provided.
Programmable interconnect channels provide interconnection networks between logic blocks, macrocells, and input/output pins. The input/output blocks (I/O blocks) provide the interface between the internal logic to the I/O pins of the device.
The composition of CPLD
CPLDs with larger logic scales generally also have built-in JTAG boundary-scan test circuitry, which allows for comprehensive and thorough system testing of programmed high-density programmable logic devices, in addition to in-system programming via the JTAG interface.
Due to the different integration processes, integration scale, and manufacturers, there are also major differences in the partition structure and logic cells of various CPLDs.
(1) EPM7128S device basic structure
EPM7128S device mainly consists of logic array block LAB, macro cell, I/O control block and programmable interconnect array PIA.
In the multi-array matrix structure, each macrocell has a programmable with array and a fixed or array, as well as a configurable flip-flop with independently programmable clock, clock enable, clear, and reset functions. Multiple LABs are connected via the Programmable Interconnect Array PIA and the global bus. Each LAB is also connected to the corresponding I/O control module to provide direct input and output channels.
(2) EPM7128S Macro Cell Structure
Each macrocell of the EPM7128S is capable of being individually configured for combinational or timing logic operation. The macrocell consists of three main parts: the logic array, the product term selection matrix, and the programmable registers. The programmable registers can be programmed to bypass and implement combinational logic according to the logic needs. If used as registers, the corresponding programmable logic device development software will select the effective register operation according to the design logic needs to minimize the device resources used for the design.
The XCR3064XL device macrocell structure consists of function blocks and I/O cells connected by zero power interconnect arrays, with each logic block containing 16 macrocells.
The identification and classification of FPGAs and CPLDs are mainly based on their structural characteristics and operating principles.
The usual classification methods are:
Devices that are structured in a product term structured manner to form a logical behavior are called CPLDs, such as Lattice's ispLSI series, Xilinx's XC9500 series, Altera's MAX7000S series, and Lattice's (formerly Vantis) Mach series.
Devices that are structured in a look-up table method to form the logic behavior are called FPGAs, such as Xilinx's SPARTAN series, Altera's FLEX10K or ACEX1K series, etc.
Although FPGA and CPLD are both programmable ASIC devices and have many common features, they have their own characteristics due to the differences in the structure of CPLD and FPGA:
① CPLD is more suitable for completing various algorithms and combinational logic, and FPGA is more suitable for completing timing logic. In other words, FPGA is more suitable for structures with rich flip-flops, while CPLD is more suitable for structures with limited flip-flops and rich product terms.
②The continuous wiring structure of CPLD determines that its timing delays are uniform and predictable, while the segmented wiring structure of FPGA determines the unpredictability of its delays.
CPLD is programmed by modifying the logic function with fixed interconnect circuit, while FPGA is programmed by changing the wiring of internal wires; FPGA can be programmed under the logic gate, while CPLD is programmed under the logic block.
④FPGAs are more integrated than CPLDs and have more complex wiring structures and logic implementations.
⑤ CPLD is more convenient to use than FPGA. CPLD is programmed by E2PROM or FASTFLASH technology, no external memory chip is needed, easy to use. While the FPGA programming information needs to be stored in external memory, the use of complex methods.
(6) CPLDs are faster than FPGAs and have greater time predictability. This is due to the fact that FPGAs are programmed at the gate level and use distributed interconnections between CLBs, while CPLDs are programmed at the logic block level and their interconnections between logic blocks are collective.
CPLD is mainly based on E2PROM or FLASH memory programming, which can be programmed up to 10,000 times, and has the advantage that the programming information is not lost even when the system is powered off.
CPLD can be further divided into two categories: programming on the programmer and programming in the system. FPGA is mostly based on SRAM programming, and the programming information is lost when the system is powered off, and every time when the device is powered on, the programming data needs to be re-written from outside the device to the SRAM. The programming data needs to be rewritten into SRAM from outside the device each time it is powered up. The advantage is that it can be programmed any number of times and can be programmed quickly in the work, thus achieving dynamic configuration at the board level and system level.
⑧ CPLD confidentiality is good, FPGA confidentiality is poor.
⑨ In general, the power consumption of CPLD is greater than that of FPGA, and the higher the integration level, the more obvious it is.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 