Level of integration 

As illustrated in the diagram, electronic system integration is divided into three levels: on-chip integration, in-package integration, and PCB  board-level integration.

Figure. 1

The transistor Transistor, often known as the functional cell, is the most basic unit integrated on the chip (Function Cell). The chip is made up of a huge number of functioning cells that are connected together.

The bare chip or chiplet completed in the previous stage, which we call the function unit, is the basic unit incorporated in the package (Function Unit). To build a  SiP, these functional units are integrated into the package.

The package or  SiP completed in the previous stage, which we term  MicroSystem, is the basic unit integrated on the PCB. These microsystems are incorporated into larger-scale systems via PCB  integration.

It can be seen that the degree of integration is carried out step by step, with the functions of each level of integration being continually improved on the previous level, and the scale being continually expanded.

The operations of the electronic system have been largely complete at the PCB  level, and the scale has been increased to the point where it can be controlled by humans. With the addition of other components, it forms the most widely used system, the Common System, which includes our daily interactions with a mobile phone or computer.

On-chip integration

Because it is the smallest functional unit that cannot be subdivided, the transistor on the chip is referred to as a functional cell.

The number of working cells has also become a powerful indication of the system's evolved nature. The human body has between 40 and 60 trillion cells. If the system aspires to be a human-like intelligent system, the functional cells it contains may need to increase by an order of magnitude.

Transistors can only be made smaller and smaller in order to integrate more functional cells. Transistors are one billion times smaller today than they were when the original transistor was conceived, yet their core function has not altered.

We must first develop functional cells and then integrate them together in order to incorporate on a chip. How are these transistors produced and incorporated as functioning cells? We need to understand three sorts of materials and three types of processes from a minimalist standpoint.

Conductors, semiconductors, insulators

The materials employed in modern integrated circuits practically exhaust the periodic table of elements, despite the fact that there are many materials on the chip. Conductors, semiconductors, and insulators are the three kinds of materials.

Because it is variable, it can sometimes become a conductor (on), allowing electrons to pass through, and sometimes it can become an insulator (off), blocking electron passage. The most important of these is naturally a semiconductor, which, because it is variable, can sometimes become a conductor (on), allowing electrons to pass through, and sometimes it can become an insulator (off), blocking electron passage. And, by building a particular structure and controlling it with current or voltage, this change may be controlled.

The conduction band overlaps with the valence band in a conductor, there is no forbidden band, and electrons are easy to move, forming a current under an applied electric field; in a semiconductor, a small number of electrons can transition to the conduction band and form an electric current under an applied electric field; in an insulator, electrons cannot cross the band gap and thus cannot form an electric current.

Figure. 2

Add process, minus process, graphic transfer

There are thousands of process flows to finish the fabrication of a chip, and there are various procedures for producing chips. These procedures can be classified into three types: addition, subtraction, and pattern transfer.

Adding ingredients to the substrate is the processing step. Processing procedures include ion implantation, sputtering, chemical vapor deposition CVD, and physical vapor deposition PVD, among others.

The subtractive process is simply the removal of materials, which includes etching, chemical mechanical polishing, CMP, wafer leveling, and other subtractive processes.

Pattern transfer is the most difficult and time-consuming of the three types of processes, because each step of the addition and subtraction procedures is based on pattern transfer. Pattern transfer entails using masks, lithography, and photoresist to transfer the designed pattern to the wafer.

Graphical transfer is actually the transfer of human thinking and wisdom.

Figure. 3

To create a certain pattern on the chip, each step of the addition or subtraction procedure must be transferred before and after the operation.

These patterns are stacked in several layers, mixing semiconductors, conductors, and insulators to build a three-dimensional structure, resulting in functional cells on the wafer plane and the realization of related functions.

Three different materials combined with three different techniques may produce such a complex chip, proving the ancient adage that "one life begets two, two begets three, and three begets all things."

The product integrated on the chip is a wafer, which is the result of thousands of procedures. A chip or chip is formed after the wafer is sliced to preparation for the next level of integration.

Figure. 4

Integration within the package

Not all chips or chips need to be included in the package; in fact, a single chip can be packaged and placed directly on the PCB,  With  Moore's Law failing day by day, the integration within the package has become increasingly important, and concepts such as SiP, advanced packaging, Chiplet, heterogeneous integration, 2.5D, 3D, and other concepts have increasingly become the focus of the industry, ushering in the spring of integration within the package.

Figure. 5

Because in-package integration does not rely on semiconductor properties, the materials utilized for in-package integration can be separated into two groups: conductors and insulators. The fundamental goal of integration is to connect the chips or cores that were leftover from the previous level(on-chip integration).To construct a microsystem, the particles are combined and electrically coupled within the packaging.

There is no concept of integration in the original package, which is single-chip. Chip protection, scale amplification, and electrical connection are the three basic tasks of the classic single-chip package.

On the basis of traditional packaging, the multi-chip package represented by SiP adds three new functions: boosting functional density, shortening interconnection length, and performing system reconstruction.

The integration within the package lessens the chip's integration pressure, which is seen to be a magic weapon for delaying Moore's Law's end.

The integration difficulty is substantially lower than the integration on the chip because the package does not require the fabrication of functional cells (Transistor), but just the functional cells (chiplets) are assembled.

The high flexibility of in-package integration, which may be divided into five integration dimensions: 2D, 2D+, 2.5D, 3D, and  4D, is another benefit.

The construction of functional units represented by SiP and advanced packaging, which we might name a microsystem, is the consequence of in-package integration.

Figure. 6

Figure. 7

Integration on PCB 

The integration on PCB  should be the first in the history of electronic integration. PCB  s were first introduced 11 years before packaging and 22 years before integrated circuits.

Components were directly connected by wires prior to the invention of the  PCB,  The integration density was challenging to enhance, in addition to being quite untidy.

Although PCB  has the earliest history when compared to integrated circuits and packaging, the development of integrated technology on   PCB   is relatively slow due to package size and pin density constraints. From single-sided development to double-sided, multi-layered Board, the assembly process has also evolved from plug-in to surface mount SMT, and the assembly density is also increasing.

PCBs are now essentially double-sided mounted components, with dozens of layers on the board. Widely utilized include high-density HDI boards, rigid-flex boards, microwave circuit boards, and embedded device boards.

Integration on a PCB.  like integration in a package, does not rely on semiconductor properties, hence the materials utilized are primarily split into two categories: conductors and insulators. The major goal of integration is to re-integrate and electrically connect the micro-system modules accomplished at the previous level (package integration), and then combine them with other components to build a permanent system, such as our everyday mobile phones and computers.

Figure. 8

Figure. 9

Figure. 10

Integrated link

The three levels of electronic system integration are explained above: chip-level integration, package-level integration, and  PCB board-level integration. Each level of integration has its own set of links.

On-chip integration

Device manufacturing and metal interconnection, commonly known as front-end process FEOL  and back-end process BEOL, are the two major links in chip integration.

Manufacturing of medical devices (front-end process)

Photolithography, etching, ion implantation, sputtering, chemical vapor deposition, physical vapor deposition, chemical mechanical polishing, wafer leveling, and other process stages are used to create functional cells on a single crystal silicon wafer. Transistors, resistors, capacitors, diodes, and other electronic components The current 5nm technique can produce over 100 million transistors in a 1mm2 area.

The Front End of Line contains formation procedures like as isolation, gate structure, source and drain, and contact holes, which are all part of the transistor manufacturing process (FEOL).

Ion implantation may produce single crystal silicon, as well as N, N+, N-, P, P+, P-, and other semiconductors with varying impurity concentrations, and polysilicon can be utilized as a gate or resistor.

The larger white beam is the gate G, the shorter white beam is Fin, and its width is about 0.67 times the gate width, and the gate is flanked by the source S and Drain D in the microscope photo below.

Figure. 11

Metal interconnect (back end process)

Following the fabrication of the transistor layer, tungsten and other metal contact holes are used to connect the transistors to the first layer of wiring, and then electrical interconnections are formed using multi-layer metal wiring and vias. Aluminum wiring was utilized in earlier chips, but copper wiring is used in most modern chips.

The deposition of dielectric between interconnect lines, the production of metal lines, and the formation of lead-out pads, collectively known as the  Back End of Line, are all part of the manufacturing of multi-layer metal wiring used to connect devices such as transistors (BEOL, Back End of Line).

Metals like tungsten, copper, and aluminum are used as conductors, while insulators like silicon oxide, silicon nitride, high dielectric constant film, low dielectric constant film, polyimide, and others are used as insulators.

The shot of the metal connector lines on the chip under the microscope is shown in the figure below. As can be observed, the current method can accommodate more than 10 layers of metal wiring in a multi-layer wiring system.

Figure. 12

The more advanced the integrated circuit process becomes, the more impacts emerge in an unceasing stream due to the smaller and smaller structural size. More and more sorts of elements are employed to overcome these effects and build normal function transistors, resulting in an almost exhaustive periodic table of elements. exercise.

The schematic representation of the front-end process FEOL  and the back-end process BEOL is shown below. Transistors are first produced on a silicon substrate, after which they are connected to the chip's PAD through metal interconnects.

Figure. 13

Integration in the package

The previous packaging was rather simple, serving primarily as chip protection, scale amplification, and electrical connections. The schematic diagram looks like this. Through the  Bond Wire, the chip's PAD is connected to the package substrate or lead frame, and finally to the external pins. It can be split into  BGA, CGA,  QFP, LCC, SOP, DIP, and other packaging formats according to the pin configuration.

Figure. 14

Due to the relatively simple internal structure of traditional packaging, they are lead frames or substrates that use bonding wires to connect chip pins, whereas the external pin arrangements are diverse, so when people talk about packaging, they are referring to its various external packaging forms.

This situation has drastically changed in the era of SiP and sophisticated packaging. SiP and advanced packaging exterior packaging forms are gradually united into BGA, CGA, and other packaging forms with more pin configurations and higher interconnection density. Its structure has become increasingly sophisticated as a result of the integrated functions inside, and people's attention to packaging has shifted from external to inside packaging. As a result, we believe that innovative packaging is more significant than the exterior.

It is important to integrate additional functional units into the package in order to boost the functional density. The typical bonding wire connection approach is no longer sufficient to meet the demands. A wide range of innovative packaging technologies has been developed. Let's take a look at the most typical ones. Technology.

On-chip RDL and TSV fabrication

Wiring on the chip's surface, using the RDL (Redistribution Layer) re-wiring layer, to connect the PAD to a more loosely occupied place and create a bump, which we refer to as the XY plane extension.

The chip can then be directly installed on the substrate via the bump, a procedure known as flip chip. Take a look at the illustration below to see why it's called a flip chip.

Figure. 15

The flip-chip welding process first developed in the 1960s, and it is essentially the same age as bonding wire. It has a long history, and I don't think of it as "sophisticated packaging."

Because flip-chip chips cannot be stacked, the Z-axis cannot be extended. TSV (Through Silicon Via) technology has been developed as a through-hole technology that can traverse the entire chip body.

TSV faces a number of challenges, the most pressing of which, in my opinion, is TSV's position selection and aperture reduction.

Because the TSV must pass through the entire chip body, placement selection is critical. Poor location selection might harm internal circuit connections and transistors. In order to save as much space on the chip as possible, the aperture is likewise decreased. After all, a 1mm2 surface may hold more than 100 million transistors, and if you can't manufacture hundreds of millions, it will vanish all at once.

The current TSV technology, on the other hand, is improving and growing more powerful. According to reports, up to one million TSVs may be etched in a 1mm2 region, fully meeting the needs of high-density connectivity.

A schematic diagram of the TSV on the chip is shown below. Metal conductors can connect the chip's upper and bottom surfaces through the TSV, making it ready for chip stacking.

Figure. 16

Making TSV on the chip is too complex; only the Foundry factory can accomplish it. This type of TSV is known as  3D TSV.

People invented a TSV on the silicon substrate Interposer, known as 2.5D TSV, to raise the integration level even more.

RDL and TSV production on Interposer

A silicon interposer is a type of interposer that can give more connectivity density than regular substrates.

A typical silicon interposer, known as a 3+2 structure, has three layers of metal on top and two layers of metal on the bottom, joined by through-silicon vias in the middle.

Figure. 17

The TSV on the Interposer is typically higher in size, density, and manufacturing difficulty than the TSV on the chip. This sort of 2.5D TSV can currently be processed at the OSAT packaging and testing facility.

We can then put the chip or die on the silicon interposer after completing the interposer.

Figure. 18

Interconnect Fabrication on Substrate

We'll also need to make the packaging substrate Substrate in the next phase. Organic and ceramic packaging substrates are two of the most common types of packaging substrates.

The organic substrate is comprised primarily of organic resin and glass fiber fabric, with copper foil serving as the conductor. Epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), PI resin (polyimide resin), and other organic resins are used.

Ceramic substrates have greater mechanical and thermal qualities than organic substrates and include HTCC,  LTCC, and aluminum nitride, among others.

A typical organic substrate structure is depicted in the diagram below. The Laminate lamination method is used for the center four layers, while the Buildup lamination method is used for the two layers on the upper and lower surfaces. It's known as a 2+4+2 structure.

Figure. 19

The device is usually mounted on top of the package substrate, and the bottom is connected through  BGA and PCB, 

Device Assembly and Packaging

To create a comprehensive advanced packaging, we assemble Chiplet,  Interposer, and Substrate, then process them using advanced packaging technology.

Figure. 20

We can call the result of the integration in the package SiP or microsystem because it has the function of the system and is small in size.

Integrated links on the PCB

When the chip is fully integrated into the package, the size is insufficient, and some discrete components, such as big capacitors and transformers, are unable to be integrated. As a result,  PCB is constantly required for electronic products.

Fabrication of PCB interconnection lines

PCBs have a comparable manufacturing method to biological substrates, but their wiring density is lower and their structure is simpler.

On the PCB.  the through-hole construction is most commonly utilized. Although the blind-buried-hole structure is employed on the high-density HDI board, the through-hole is generally used in the PCB due to its simple structure and low cost.

A 6-layer through-hole construction PCB can be fixed and electrically coupled as shown in the diagram below.

Figure. 21

Component assembly on PCB

After the PCB has been processed, the packaged components must be assembled on the PCB and connected to the external plug-ins and external devices via the PCB.  as illustrated in the diagram below.

Figure. 22

Full picture from Transistor to PCB

As demonstrated below, we provide a complete view of the integration from the transistor (Transistor) to the PCB:

Figure. 23

(This image is advised for readers to save because it may be the industry's first 5-level circuit integration full picture, made by hand by Suny Li from transistor to PCB) It is not drawn to scale because it is a schematic diagram. In reality, the size has increased by nearly 1,000,000 times from transistors to PCBs.)

After the transistor (NMOS or  PMOS ) is manufactured on the silicon substrate, it is connected to the chip's metal wiring through the contact hole, then to the chip's Pad, then to the 3DTSV via RDL, and finally to the RDL on the silicon transition board via uBump. And 2.5DTSV, then link to the package substrate through Bump, then connect to the BGA via the package substrate's wire and vias, and then connect to the PCB's wiring and vias.

The whole 5-level electrical signal line from the transistor to the PCB is as follows:

Transitor→Contact→Copper→Pad→RDL¹→3DTSV→uBump→RDL²→2.5DTSV→Bump→Trace¹→Via¹→BGA→Trace²→Via²→PCB

Humans create functionalities on the integrated circuit chip through transistors, reconstruct functions and enlarge the scale on SiP or advanced packaging, and further reconstruct functions and enlarge the scale on the printed circuit board.

From transistors to printed circuit boards, the scale is increased a million times and can match that of humans.

Finally, the PCB and other components are organically merged to form a mobile phone that can be operated anytime, anyplace by modern people and a computer that is virtually difficult to leave at work.