Catalog

Ⅰ What is cache memory?

Cache memory is a computer part built on a chip that allows it more effective to access data from the memory of the computer. It serves as a temporary storage area that the processor of the device can quickly recover data from. Known as a cache, this temporary storage area is more readily accessible to the processor than the main memory pool of the machine, usually some form of DRAM.

cache memory

Cache memory is often referred to as the memory of the CPU (central processing unit) and it is normally inserted directly into the CPU chip or mounted on a different chip with a separate CPU bus link. Therefore, since it is physically close to the processor, it is more available to the processor, and able to maximize performance.

Typical bus structure of cache memory

Cache memory needs to be much smaller than primary memory in order to be close to the processor. Consequently, it has less capacity for storage. It's even more costly than main memory because it's a more difficult chip that delivers better performance.

In speed, it makes up for what it loses in size and price. Cache memory performs 10 to 100 times faster than RAM and takes just a few nanoseconds to respond to a request from the CPU.

High-speed static random access memory is the name of the real hardware used by the cache memory (SRAM). The name of the circuitry used in the primary memory of a computer is dynamic random access memory (DRAM).

It is not appropriate to confuse cache memory with the larger word cache. Caches are transient data stores that may occur in hardware as well as applications. Cache memory refers to the unique portion of the hardware that enables computers to build caches at different network levels.

Ⅱ Types of cache memory

Memory in the cache is fast and costly. Traditionally, it is defined as "levels" that determine its proximity to the microprocessor and usability. Three general levels of cache exist:

The L1 cache, or main cache, is incredibly fast but comparatively thin and is normally inserted as a CPU cache in the processor chip.

The L2 cache, or secondary cache, is always bigger than the L1 cache. The L2 cache can be embedded on a Core, or it can be on a separate chip or coprocessor, and the cache and CPU can be connected by a high-speed alternate system bus. That way, the traffic on the main system bus doesn't slow down.

Level 3 (L3) cache is specialized memory built to optimize L1 and L2 performance. L1 or L2 can be slightly faster than L3, while L3 is normally twice the DRAM level. Each core can have a dedicated L1 and L2 cache for multicore processors, but they may share an L3 cache. If an instruction is referenced by an L3 cache, it is typically raised to a higher cache level.

levels of cache

In the past, combined processor and motherboard modules were used to build L1, L2, and L3 caches. The movement has recently been towards consolidating all three memory caching stages on the CPU itself. That's why the key means of growing cache capacity have started to move from purchasing a particular motherboard with multiple chipsets and bus architectures to buying a CPU with the correct amount of optimized cache for L1, L2, and L3.

Contrary to common opinion, it won't increase cache memory to implement flash or more dynamic RAM (DRAM) on a device. As the terms memory caching (hard disk buffering) and cache memory are sometimes used interchangeably, this can be misleading. Memory caching is intended to boost storage I/O by caching data that is often referenced in a queue instead of a slower magnetic disk or tape, using DRAM or flash to buffer disk reads. On the other side, cache memory includes the CPU's read buffer.

Ⅲ Development and history of cache memory

An early version of cache memory was used by mainframes, but with the introduction of microcomputers, the hardware as it is known today started to be developed. Processor performance improved even more rapidly with early PCs than memory performance, and memory became a bottleneck, halting systems.

The idea took hold in the 1980s that a small volume of more costly, quicker SRAM could be used to maximize the performance of the less costly, slower main memory. Initially, and not always included in the motherboard, the ram cache was separate from the device processor. Usually, early PCs had between 16 KB and 128 KB of cache memory.

Intel added 8 KB of memory to the CPU with 486 processors as Level 1 (L1) memory. In such devices, 256 KB of additional Level 2 (L2) cache memory was included. On the high-end, Pentium processors saw the external cache memory double to 512 KB again. The internal cache memory was also split into two caches: one for instructions and the other for data.

Introduced in 1995, processors based on Intel's P6 microarchitecture were the first to integrate L2 cache memory into the CPU and allow all of the cache memory of a device to run at the same clock speed as the processor. L2 memory external to the CPU was accessed prior to the P6 at a much slower clock speed than the rate at which the processor ran and greatly hindered machine performance.

A write-through cache architecture was used by early memory cache controllers, where data inserted into the cache was often modified immediately in RAM. This reduced the lack of records but also hindered operations. The write-back cache architecture was developed with later 486-based PCs, where RAM is not instantly modified. Instead, data is kept in the cache, and RAM is only modified at particular times or under certain conditions when data is incomplete or old.

Ⅳ Mapping and Data writing of cache memory

1.Cache memory mapping

Caching configurations continue to evolve, but three different configurations typically operate for cache memory:

Each block mapped to exactly one cache memory location has a direct-mapped cache. Conceptually, a direct-mapped cache is like rows in a three-column table: the cache block containing the actual fetched and stored data, a tag containing all or part of the fetched data address, and a flag bit indicating the presence of a valid bit of data in the row entry.

Completely associative cache mapping is similar to direct structural mapping, but as with direct mapping, it requires a memory block to be assigned to every cache location rather than a prespecified cache memory location.

Set associative cache mapping can be seen as a combination between the direct mapping and entirely associative mapping in which a subset of cache positions is assigned to each block. It is often referred to as N-way set associative mapping, which requires all of the 'N' locations in the L1 cache to be cached to a location in the main memory.

2.Data writing policies

Using a number of methods, data may be written to memory, but the two key ones involving cache memory are:

Write-through there. Data are concurrently written to both the cache and the main memory.

To write-back. Data is only initially written to the cache. Data will then be written to the primary memory, but this need not occur and does not inhibit the connection from happening.

Data integrity and reliability are influenced by the way data is written to the cache. For eg, further writing needs to happen by using write-through, which creates lag upfront. Operations can be more effective when using write-back, but data may not be compatible between the main and cache memories.

The way a system determines the accuracy of knowledge is by testing the dirty bit of memory. The dirty bit is an external bit used in memory blocks that show how the data has been changed. If data enters the register file of the processor with an active dirty bit, this means that it is not up-to-date and elsewhere there are more modern copies. In a write-back situation, this scenario is more likely to happen, since the data is written asynchronously to the two storage regions.

Ⅴ Comparison of cache memory, main memory, and virtual memory

1.Cache memory vs. main memory

DRAM functions as the primary memory of a computer, running calculations on data collected from storage. DRAM and cache memory are also volatile memories that, when the power is switched off, lose their content. On the motherboard, DRAM is mounted, and the CPU accesses it via a bus link.

Currently, DRAM is around half as fast as cache memory L1, L2, or L3, and much less costly. It allows quick access to data than flash storage, hard disk drives (HDD), and storage for tape. In the last few decades, it has been used to provide a place for storing regularly accessed disk data to boost I/O performance.

A few milliseconds, DRAM must be renewed. It is not necessary to update the cache memory, which is also a form of random access memory. To allow the processor the fastest possible access to memory locations, it is integrated directly into the CPU and gives nanosecond speed access time to commonly referenced instructions and data. SRAM is simpler than DRAM, but it is still more difficult to produce because it's a more complicated chip.

2.Cache memory vs. virtual memory

There is a restricted amount of DRAM on a computer and much less cache memory. It's possible for memory to be entirely used while a big program or many programs are running. The operating system (OS) of the computer will build virtual memory to compensate for a lack of physical memory.

The OS briefly switches unused data from DRAM to disk storage in order to accomplish this. By using active memory in DRAM and inactive memory in HDDs to form contiguous addresses that contain both an application and its records, this method increases virtual address space. Digital memory allows a machine to concurrently execute bigger programs or multiple programs, and each program functions as if it has infinite memory.

The OS splits memory into page files or swap files that contain a certain number of addresses in order to copy virtual memory into physical memory. Such pages are stored on a disk and the OS copies them from the disk to the main memory when they are needed and converts the virtual memory address into a physical one. A Memory Management Unit performs these translations (MMU).