Ⅰ STM32U5 Overview

STM32 low-power series products from STM32L5 to STM32U5, although the core is the same, all use the Arm v8 architecture of Cortex-M33, but its process, circuit design, and other aspects have made a huge innovation, and the use of the new 40nm technology platform, which is also an important support platform for future ST low-power MCU technology.

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Historically, the ultra-low power product line has been a strategic product line for STM32. Since 2007, when ST released the first general-purpose microcontroller based on the Cortex-M core, ST expanded the Cortex-M family of microcontrollers into the ultra-low power segment in 2009.

The STM32U5 can be used in industrial smart flow meters, health and fitness wearables, medical monitoring devices, POS payment terminals, and other scenarios where both power consumption and security are highly required.

As the first product of the U series platform, what new features have the STM32U5 implemented?

Compared with STM32L5, some updates of STM32U5

Ⅱ Unification of low power and high performance

EEMBC ULPMark

First is the EEMBC ULPMark score, which covers power consumption analysis in different modes, and STM32 is the only brand to publish all 4 scores, which also proves its confidence in low power consumption across the scenario.

Customers have different application scenarios, some for high load work and some for long standby applications, so simply comparing µA/MHz does not work for every customer. By providing scores for different work scenarios, customers can better refer to.

In addition to a more advanced 40nm process and improvements in both leakage and dynamic current, the STM32U5 has improved power management modes with the addition of Low Power Background Autonomous Mode (LPBAM), and a number of peripherals and functions that can operate at low power.

The STM32U5 has 16kB SRAM as storage space for Low Power Background Autonomous Mode, to which peripheral data such as I2C, SPI, serial, ADC, etc. can be transferred via LPDMA while the CPU is asleep, and then the CPU can be woken up for one-time batch processing when the data accumulates to a certain amount. By avoiding frequent wake-up of CPU, thus achieving the purpose of power-saving. According to the model of classical data acquisition and wake-up processing tested by ST, the number of CPU wake-ups can be turned into 1/10 of the original one.

Second, it integrates high frequency DC/DC and LDO. By integrating high frequency DC/DC, the conversion loss from VDD to the core power supply can be reduced to achieve the most optimized dynamic power consumption and the fastest dynamic response. And by LDO, the drawback of slow DC/DC start-up time can be solved.

Thirdly, it is similar to LPRAM, which provides partitioned FLASH and SRAM. Users can turn off and turn on on-demand the less frequently used Flash according to the application scenario, or reduce power consumption by lowering the FLASH read speed.

As shown in the figure, the rich combination of low-power modes allows users to choose more flexibly.

Block diagram of some low-power modes

In addition to low power consumption, high performance is also a major feature of the STM32U5. The processor up to 160MHz has made the STM32U5 series achieve a performance score of 240DMIPS and 651Coremark. The previous generation STM32L5, which also uses the Cortex-M33 core, is clocked at 110MHz. At the same time, in order to further enhance performance, STM32U5 also integrates FMAC and Cordic math accelerators. Art accelerator (8 kB instruction cache, 4 kB data cache) for optimizing instruction and data throughput cache on internal and external storage, and Chrom-Art, a 2.5D graphics accelerator for resource-constrained situations.

Ⅲ More Functional Safety and Information Security

The Cortex-M33 was developed specifically for high data security applications with the Arm v8 architecture, incorporating TrustZone technology, just to meet the high-security applications of the Internet of Things, but in fact, the MCU is not currently secure enough.

That's exactly why STM32U5 adds additional security features on top of L5 to ensure the security of IoT. The kernel isolation or TrustZone support alone is obviously not enough. Therefore, in addition to kernel isolation, the STM32 is designed for isolated configurations of the product's internal storage, buses, and peripherals.

Isolation of the STM32U5

In addition, the STM32U5 adds more security encryption features and a fully controllable multi-layer protection state machine. The storage protection is especially designed for internal storage tampering, with additional OTP space and active tampering for active anti-infringement.

PSA Level 3 requires protection against both software and hardware attacks, so the STM32U5 specifically adds an AES module to prevent border attacks.

Arm's requirements for PSA Level 3 certification require that the chip also needs an immutable root of trust under a secure framework. With the root of trust, the secure boot supported on the STM32U5 can function based on this secure foundation. For such a secure boot feature, ST provides relevant reference codes that can help users implement related secure boot, secure firmware loading, and secure firmware update.

If the TF-M (Trusted Firmware for Cortex-M) architecture is used, in addition to the TrustZone, the internal services and software can be separated into Trusted and Untrusted Zones, and administrator and user privileges can also be set in the software permissions. Under the administrative authority, there are also PSA modular local security services available in the Trust Zone, which include more functional modules related to encryption and decryption, secure storage, Trust Zone initialization, and certificate initialization. These are important for passing the PSA Level 3 certification and for implementing a TF-M trusted firmware framework.

The STM32U5 also provides secure firmware loading. After the customer has designed the software and licensed it for third-party production, there is no way to guarantee the software security. ST helps the user to strictly control the security of the burned firmware and the number of burned copies in a third-party burn-in environment through an internal SFI production process.

Because of the enhanced anti-tampering and software protection features, the STM32U585 is also suitable for controlling PIN Transaction Security (PTS) devices, which must meet the technical requirements of the Payment Card Industry Security Standards Council (PCI SSC). As a secure general-purpose MCU, the STM32U585 provides developers with a total solution to simplify the design and production of point-of-sale and self-service payment terminals.

Products that receive the "PTS Officially Approved Device" logo typically require a security chip dedicated to defending against inline and sideband attacks, as well as a separate MCU to manage the keyboard, display, and USB connectivity. The STM32U585 now integrates all of these functions in a single chip, simplifying product design and optimizing production logistics from procurement and inventory management to final assembly. End manufacturers can also test and certify products to applicable standards such as PCI PTS v6 faster and more easily.

Ⅳ More Powerful Storage Units

While processing speed is one aspect of MCU selection, storage is another important metric.

The STM32U5 has further expanded the storage space in addition to the low power consumption achieved by using partitioning.

Storage layout and processing main frequency of successive generations of low-power STM32 MCUs

As shown in the figure, the STM32U5's Flash planning from 128kB to 4MB will greatly expand the user's selection. At the same time, the Flash contains up to 0.5MB with 100,000 times read/write capability to improve the reliability guarantee for user data storage, while the rest is conventional 10,000 times.

The SRAM, on the other hand, is 786kB and supports ECC, thus satisfying critical security applications.

The STM32U5 also features the ever-present variable static memory controller FSMC, as well as OctoSPI, thus supporting more flexible external storage expansion.