Since Samsung's official announcement of mass production of 3nm chips, in competition with TSMC and Intel advanced process to gain a time advantage, the other two manufacturers in the battle for advanced packaging has also ushered in the latest progress. Foreign media sources show that Samsung has set up a semiconductor packaging working group to strengthen cooperation with large customers.

In the context of the growing demand for performance in the semiconductor field and the gradual failure of Moore's Law, advanced packaging has become a new power point. It is reported that through advanced packaging technology to heterogeneous integration of multiple chips, or the traditional large chip split into multiple small chips, and through advanced packaging technology to integrate the Chiplet program, can greatly enhance the function and reduce costs. Thus Samsung, TSMC, Intel for advanced packaging technology seems to be imperative.

Samsung

According to foreign media sources, Samsung's device solutions (DS) department has been set up in a direct co-CEO Kyung Kye-hyun semiconductor packaging working group, the purpose is to strengthen cooperation with major foundry customers in the field of packaging. According to the news, the group brings together test and system packaging engineers from Samsung's DS Division, researchers from the Semiconductor R&D Center, and personnel from the memory and foundry divisions, and is expected to come up with more advanced packaging solutions.

In terms of advanced packaging technology, Samsung earlier launched the 2.5D packaging technology I-Cube, and in August 2020 announced the launch of a new generation of 3D packaging technology - X-Cube, which can stack different chips based on TSV silicon perforation technology and is currently used in 7nm and 5nm processes. In recent years, Samsung has accelerated its efforts in advanced packaging, and in late 2021, Samsung again announced that it had developed the latest 2.5D packaging solution, H-Cube, and said it was also developing the latest "3.5D packaging" technology. But compared with TSMC and Intel's packaging technology and the commercial use of the situation, at present, Samsung is still in the backward situation.

Intel

Intel is unique in advanced packaging technology. As early as the end of 2018, Intel launched the industry's first 3D logic chip packaging technology, Foveros 3D, which enables the stacking of logic chips of different processes on logic chips.

At Intel's Intel Accelerated technology briefing in 2021, Intel adopted a new naming system for Intel 7 (previously called 10nm Enhanced SuperFin), Intel 4 (previously called Intel 7nm), Intel 3, and Intel 20A.

With the announcement, there are four development lines of Intel on packaging technology, which are EMIB technology, Foveros technology, Foveros Omni technology and Foveros Direct technology.

Among them, EMIB will be the first technology to adopt 2.5D embedded bridging solution, in the recently held Intel On Industry Innovation Summit, Intel's fourth-generation Xeon processor Sapphire Rapids using Intel 7 process was unveiled, and became the first product to use EMIB packaging technology; Foveros will use wafer-level packaging technology to provide the first ever 3D stacking solution; Foveros Omni will make die-to-die interconnects and modular designs more flexible through high-performance 3D stacking technology; Foveros Direct enables copper-to-copper bonding transformation and also enables low-resistance interconnects.

TSMC

TSMC has been laying out 2.5D and 3D advanced packaging technology for more than 10 years, and in recent years, its update iteration speed has accelerated, and the continuous launch of its fist products has attracted the attention of the industry. In general, TSMC has integrated 2.5D and 3D advanced packaging-related technologies into the "3DFabric" platform, which allows customers to freely select the front-end technologies including 3D SoIC InFO-3D, and the back-end assembly and testing-related technologies including 2D/2.5D integrated fan-out (InFO) and 2.5D CoWoS family.

Recently, TSMC held the TSMC Technology Symposium 2022 in Santa Clara, California, and announced two major breakthroughs in the 3D Fabric platform. Wafer (CoW) technology to stack SRAM as a Level 3 cache; and second, a breakthrough intelligent processing unit using Wafer-on-Wafer (WoW) technology stacked on top of a deep trench capacitor chip.

TSMC said that support for N5 technology is planned for 2023, as N7 chips for CoW and WoW are already in production. In addition, to meet customer demand for system integration chips and other TSMC 3D Fabric system integration services, the company will build the world's first fully automated 3D IC advanced packaging facility in Zhunan, with production expected to begin in the second half of this year.