TSMC, a leading foundry, recently launched the 2022 TSMC Technology Symposium North America to share process technology development blueprints and future plans. One of the keys is the advanced process nodes such as 3nm (N3) and 2nm (N2). Within a few years these nodes will be used to manufacture advanced CPUs, GPUs and SoCs.

N3: Five process technologies for the next three years

Foreign media reports that as manufacturing technologies become more complex, development, research and development time is also increasing. No longer see TSMC and other foundries emerge with brand new nodes every two years. For the most advanced N3 process, TSMC's import timeline has expanded to about 2.5 years, and the N2 process has been extended to 3 years.

The extended lead time means TSMC needs to provide N3 node enhancements to meet customer demand, as customers continue to improve performance per watt and crystal density. Another reason is that the N2 node relies on a nanosheet structure to reach a new gate surround field effect transistor (GAA FET), which increases costs and necessitates new design methods, new IP and other changes. While advanced chip developers will soon move to the N2 process, TSMC's general customers continue to use various N3 process technologies.

TSMC's technical seminar also addressed the four N3 node extensions to be introduced in a few years, bringing the N3 node to a total of five processes N3, N3E, N3P, N3S and N3X. The N3 extensions are improved technologies for ultra-high performance applications, with higher performance quantities of crystal density, and higher enhancement voltages. All technologies support the FinFlex architecture, TSMC's secret weapon that dramatically enhances design flexibility and allows chip designers to precisely optimize performance, power and cost.

1. N3 and N3E: On track for volume production

TSMC's first 3nm-class node, called N3, is expected to be in volume production in the second half of the year, with physical products to be delivered to customers in early 2023. Primarily targeted at early-use customers, it can invest in leading designs and benefit from the performance, power, and area (PPA) advantages of advanced nodes. However, it is tailored for specific types of applications, so the N3 node has narrow applicability and may not be suitable for all applications.

This leaves room for the N3E process to play a role in improving performance as well as reducing power consumption and increasing applicability with a view to increasing yields. What needs to be considered is the slightly lower logic density. Compared to the N5 process, the N3E crystal density is 1.6 times higher and reduces power consumption by 34% at the same computing speed and complexity, or improves performance by 18% at the same power and complexity. TSMC information shows that N3E is faster than N4X computing speed, but supports ultra-high drive current and 1.2V above voltage, although the performance is better, power consumption is higher.

N3E process chip risk trial production will begin in the second or third quarter, and mass production will begin in mid-2023. Commercial N3E process chips will be available by the end of 2023 or early 2024.

2. N3P, N3S and N3X: performance/density improvement

The N3 node extension is not limited to N3E. The N3P process, a performance-enhanced version of the N3 process, will be launched in 2024, in addition to N3S, a crystal density-enhanced version of the N3 process. TSMC did not reveal what has been changed or enhanced compared to the N3 process, and the development blueprint does not even have the N3S process to confirm performance.

The N3X process is the successor to the N4X process, but also did not disclose detailed information, only that the N3X process supports high drive current and voltage, the market speculation that N3X can use the back side of the power supply. Currently talking about the FinFET technology process nodes, TSMC expects the N2 node to use the nanometer chip architecture GAAFET technology to reach the back side of the power supply, the market speculation can be achieved is not certain. However, the N3X process to enhance the voltage and performance, when TSMC will have many advantages.

3、FinFlex: N3 process secret weapon

Speaking of enhanced performance, it is impossible not to mention TSMC's N3 process secret weapon FinFlex technology. Simply put, FinFlex allows chip designers to precisely design structural modules to have higher performance, higher density and lower power consumption. TSMC FinFlex technology allows chip designers to mix and match various types of FinFETs within a module to precisely tailor performance, power consumption and chip area. For complex structures like CPU cores, optimization has many opportunities to improve core performance while also optimizing the die size of the chip.

While FinFlex technology is not a replacement for performance, density, and voltage changes after node upgrades, FinFlex appears to be a good way to optimize performance, power, and cost. TSMC's N3 node process will enable FinFET technology to more closely resemble GAAFET flexibility using nanosheets through FinFlex, including providing adjustable channel widths to achieve higher performance or lower power consumption.

To conclude, like the N7 and N5 nodes, N3 will become another persistent node family for TSMC. Especially with TSMC's 2nm node moving to nanochip GAAFET technology, the 3nm node family will be the last family of classic advanced FinFET technology that many customers are scheduled to adopt for several years or more. In turn this is the reason why TSMC prepares multiple versions of N3 process families and FinFlex technology for different applications, providing more flexibility for chip designers.

N2: Mass production in 2025

At the 2022 Technology Forum, TSMC debuted its next-generation advanced process, N2, which represents another significant advancement of N3, with a 10-15% speed increase at the same power or 25-30% power reduction at the same speed, opening a new era of efficient performance.

TSMC's N2 technology will use a nanosheet transistor architecture to provide full-node improvements in performance and power efficiency, thereby supporting next-generation product innovation for TSMC customers. In addition to the mobile computing benchmark version, the N2 technology platform includes a high-performance version, as well as a comprehensive small-chip integration solution. n2 is scheduled to begin production in 2025.