Arm Cortex-M3 processor, running at CPU frequencies of up to 180 MHz

Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions

Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)

Non-maskable Interrupt (NMI) input

JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points

Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support

System tick timer

Up to 1 MB on-chip dual bank flash memory with flash accelerator

16 kB on-chip EEPROM data memory

136 kB SRAM for code and data use

Multiple SRAM blocks with separate bus access

64 kB ROM containing boot code and on-chip software drivers

64 bit of One-Time Programmable (OTP) memory for general-purpose use

Crystal oscillator with an operating range of 1 MHz to 25 MHz

12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature andvoltage (1 % accuracy for Tamb = 0 °C to 85 °C)

Ultra-low power RTC crystal oscillator

Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL can be used with the High-speed USB,the third PLL can be used as audio PLL

Clock output

State Configurable Timer (SCT) subsystem on AHB

Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like timers, SCT, and ADC0/1

Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to52 MB per second

10/100T Ethernet MAC with RMII and MII interfaces and DMA support for highthroughput at low CPU load. Support for IEEE 1588 time stamping/advanced timestamping (IEEE 1588-2008 v2)

One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY (USB0)

One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to an external high-speed PHY (USB1)

USB interface electrical test software included in ROM USB stack

Four 550 UARTs with DMA support: one UART with full modem interface; oneUART with IrDA interface; three USARTs support UART synchronous mode and asmart card interface conforming to ISO7816 specification

Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge

Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport

One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/Opins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s

One standard I²C-bus interface with monitor mode and standard I/O pins

Two I²S interfaces with DMA support, each with one input and one output

External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices

LCD controller with DMA support and a programmable display resolution of up to1024H x 768V. Supports monochrome and color STN panels and TFT color panels;supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixelmapping

SD/MMC card interface

Eight-channel General-Purpose DMA controller can access all memories on theAHB and all DMA-capable AHB slaves

Up to 164 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors

GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport

Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources

Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins

Four general-purpose timer/counters with capture and match capabilities

One motor control PWM for three-phase motor control

One Quadrature Encoder Interface (QEI)

Repetitive Interrupt timer (RI timer)

Windowed watchdog timer

Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers

Event recorder with three inputs to record event identification and event time; canbe battery powered

Alarm timer; can be battery powered

One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s

Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.Up to eight analog channels total. Each analog input is connected to both ADCs

Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator forthe core supply and the RTC power domain

RTC power domain can be powered separately by a 3 V battery supply

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down

Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals

Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain

Brownout detect with four separate thresholds for interrupt and forced reset

Power-On Reset (POR)