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Ball Grid Array (BGA) PCB design requires careful planning because the electrical connections are hidden beneath the component rather than arranged around its edges. A BGA package uses an array of solder balls to connect an integrated circuit to the PCB, allowing many connections within a compact area. However, smaller ball pitches, limited routing space, and hidden solder joints create challenges during layout and manufacturing. To build a reliable BGA PCB, you need to consider more than the number of solder balls. Pad dimensions, trace spacing, power delivery, heat dissipation, and assembly requirements all affect the finished design.
Figure 1. Comparison of Three BGA Package Types: Plastic (PBGA), Ceramic (CBGA), and Tape-Based (TBGA)
BGA package specifications affect PCB space, routing difficulty, and manufacturing requirements. Before designing a PCB, you should check the ball pitch, ball count, package dimensions, and recommended land pattern to confirm that the selected component is compatible with the intended board design.
Three specifications influence BGA PCB design:
• Ball pitch: Center-to-center spacing between adjacent solder balls. Smaller pitches leave less space for PCB routing.
• Ball count: Number of solder connections, including signals, power, and ground.
• Package dimensions: Physical body size, which affects component placement and available PCB area.
The following table compares actual Texas Instruments BGA packages.
| Device (package) | Ball pitch | Ball count | Body size | Routing considerations |
| TMS320C6743 (ZKB) | 1.0 mm | 256 | 17 × 17 mm | More space between connections |
| AM3358 (ZCZ) | 0.8 mm | 324 | 15 × 15 mm | Tighter trace and spacing requirements |
| AM625SIP (AMK) | 0.5 mm | 425 | 13 × 13 mm | May require finer PCB fabrication features |
Smaller pitches can reduce component size but make routing more restrictive. However, PCB layer count depends on the ball arrangement, signal assignments, and routing capabilities, not pitch alone.
BGA connections involve three different dimensions: solder ball diameter, PCB copper land-pad diameter, and solder mask opening. These dimensions are not necessarily equal and should follow the selected manufacturer's recommendations.
AMD UG1099 provides the following dimensions for supported BGA packages. [2]
| Ball pitch | Copper land-pad diameter | Solder mask opening |
| 1.0 mm | 0.50 mm | 0.53 mm |
| 0.92 mm | 0.51 mm | 0.53 mm |
| 0.8 mm | 0.40 mm | 0.40 mm |
| 0.5 mm | 0.26 mm | 0.28 mm |
Figure 2. BGA Solder Ball, Copper Pad, and Solder Mask Opening Dimensions. Example based on AMD's 1.0 mm pitch recommendations
These values apply to the packages covered by AMD's guide. Other devices may require different land patterns, even at the same pitch.
Before choosing a BGA, verify that the PCB manufacturer supports the required trace width and spacing, via dimensions, layer stack-up, solder mask registration, and assembly tolerances.
For example, a 0.5 mm pitch BGA with a 0.26 mm copper pad leaves a nominal 0.24 mm gap between adjacent pads.
A trace measuring 0.08 mm wide with 0.08 mm clearance on each side requires:
Required space = 0.08 + 0.08 + 0.08 = 0.24 mm
This fits the nominal gap but leaves no allowance for additional dimensional variation. A supplier limited to 0.10 mm traces and clearances cannot accommodate the same arrangement.
Fine-pitch packages may therefore require tighter fabrication tolerances or advanced PCB processes. Confirm manufacturing capabilities before beginning layout to avoid costly redesigns.
An accurate BGA footprint must match the manufacturer's package drawing and recommended land pattern. Incorrect pad locations, ball assignments, or solder mask openings can cause assembly defects and electrical connection failures.
Use the manufacturer's mechanical drawing to verify the PCB CAD footprint before routing.
For example, the Texas Instruments ZVB0176A is a 176-ball NFBGA package with a 0.4 mm pitch, a nominal 7 × 7 mm body, and a recommended 0.23 mm copper land-pad diameter. [3]
Follow these verification steps:
- Confirm the package code: Match the exact device package and drawing revision.
- Check physical dimensions: Compare body size, ball pitch, array positions, and mechanical tolerances with the CAD footprint.
- Verify ball locations: Check row and column labels, A1 orientation, and intentionally vacant ball positions.
- Compare land patterns: Verify copper pad dimensions and solder mask openings against the manufacturer's recommended layout.
- Check pin mapping: Confirm that each schematic symbol pin matches the correct footprint ball and device signal.
Figure 3. BGA Footprint Verification Using the TI ZVB0176A Package
The ZVB0176A has 176 populated ball positions and 49 vacant positions within its 15 × 15 grid. Pay particular attention to A1 orientation, because the package bottom view and PCB top view use different viewing directions. Finish by running the CAD software's electrical rule check (ERC) and design rule check (DRC). [3]
BGA land patterns use two main pad types:
• Solder-mask-defined (SMD): The solder mask overlaps the copper pad edges, determining the exposed soldering area.
• Non-solder-mask-defined (NSMD): The mask opening is larger than the copper pad, exposing its top surface and sidewalls.
Figure 4. SMD vs NSMD BGA Land Pattern Comparison.
| Design factor | SMD pads | NSMD pads |
| Exposed pad area | Defined by mask opening | Defined by copper pad |
| Manufacturing tolerance | More sensitive to mask registration | Better copper dimensional control |
| Solder wetting | Primarily exposed pad surface | Pad surface and sidewalls |
| Mechanical reliability | Can improve resistance to certain pad-cratering failures | Often preferred for solder joint reliability |
| Typical application | Package-specific or mechanically demanding designs | Common BGA PCB land patterns |
AMD and Analog Devices generally recommend NSMD pads because of improved dimensional control and additional solder-wetting area. However, SMD pads may be preferable for certain mechanical reliability requirements. [2][4]
Neither design is universally more reliable. Follow the selected package's recommendations and required reliability specifications.
PCB surface finish, solder mask accuracy, and stencil compatibility affect BGA solder joint quality.
• Surface finish: ENIG (Electroless Nickel Immersion Gold) and OSP (Organic Solderability Preservative) are commonly recommended for BGA assemblies. ENIG provides a uniform plated solderable surface, while OSP protects exposed copper until assembly. [4]
• Solder mask clearance: Openings must match the selected land pattern and account for mask registration tolerances. Insufficient clearance can unintentionally cover copper, while excessive openings may reduce the solder mask between adjacent pads.
• Stencil requirements: Solder paste apertures must align with the completed land pattern. For example, TI's ZVB0176A package drawing provides an example using 0.23 mm circular apertures with a 0.10 mm thick stencil. [3]
Before releasing the design, confirm the surface finish, solder mask geometry, and stencil aperture requirements with the PCB fabricator and assembler. Detailed solder paste printing, placement, and reflow processes are covered in Section 5.
BGA fanout routing connects solder pads to PCB traces and internal layers. The routing method depends on ball pitch, pad dimensions, signal density, and PCB manufacturing capabilities. As pitch decreases, engineers have less space for traces and vias, making routing and layer planning more challenging.
Dog-bone fanout uses a short trace to connect a BGA solder pad to an offset via. Via-in-pad places the via directly inside the solder pad, allowing the connection to reach another PCB layer without an external escape trace. [2]
| Feature | Dog-Bone Fanout | Via-in-Pad |
| Via location | Outside the solder pad | Within the solder pad |
| Routing space | Requires space for an offset via | Frees space around the pad |
| Suitable applications | BGAs with sufficient breakout space | Dense, fine-pitch BGAs |
| Fabrication | Conventional processes where feasible | Specialized filled and capped via processing for solderable pads |
Dog-bone routing is useful when conventional fabrication can accommodate the required pad and via spacing. Via-in-pad becomes advantageous when the layout needs greater escape density.
Smaller BGA pitch reduces the space available between adjacent solder pads. AMD UG1099 provides the following routing dimensions for its example designs. [2]
| Parameter | 0.8 mm pitch | 0.5 mm pitch |
| PCB solder land diameter | 0.40 mm | 0.27 mm |
| Space between adjacent pads | 0.40 mm | 0.23 mm |
| Example trace width | 4 mil | 3 mil |
| Example pad-to-trace clearance | 5 mil | 3 mil |
| Two traces between adjacent pads | Supported in example | Not supported in example |
Example calculation:
Available space = Ball pitch − PCB pad diameter
• 0.8 mm BGA: 0.8 − 0.40 = 0.40 mm
• 0.5 mm BGA: 0.5 − 0.27 = 0.23 mm
For the 0.5 mm example, one 3 mil trace with 3 mil clearance on both sides requires approximately 0.229 mm. This nearly consumes the entire available channel, leaving essentially no design margin. AMD also warns that not every manufacturer supports 3 mil pad-to-trace clearance. [2]
These dimensions demonstrate routing feasibility for the specified example, not universal PCB fabrication limits.
The number of signal-routing layers depends on the number of signals requiring breakout and the available routing channels.
A simplified estimate is:
L = NsC x R
Where:
• L = estimated signal-routing layers
• Ns= number of signals requiring breakout
• C = available routing channels per layer
• R = signal traces per channel
Example: AMD 530-ball, 0.5 mm BGA
AMD estimates that approximately 60% of BGA balls are signals for the device families covered by UG1099. Its 530-ball example has 88 routing channels.
• Estimated signals: 530 × 0.60 = 318
• One trace per channel: 318 ÷ 88 = 3.61 → 4 signal layers
• Two traces per channel: 318 ÷ 176 = 1.81 → 2 signal layers
These calculations match AMD's published estimates. However, routing two traces per channel requires suitable geometry and fabrication capability; it is not automatically feasible between adjacent 0.5 mm BGA pads.
The calculation is an initial planning estimate. Actual requirements depend on usable I/O count, pin assignments, routing restrictions, and power distribution. Total PCB layers also include ground and power planes.
High-density interconnect (HDI) technology becomes useful when conventional traces and through-hole vias cannot provide sufficient escape routes.
The main interconnect options include:
- Microvias: Small, shallow interconnects commonly used between adjacent layers in HDI constructions.
- Blind vias: Connect an outer PCB layer to one or more internal layers without passing through the entire board.
- Buried vias: Connect internal layers without reaching external surface.
For example, a 0.8 mm BGA may be routable using conventional dog-bone fanout. A dense 0.5 mm BGA may require via-in-pad microvias to reach inner layers while preserving routing space. However, pitch alone does not determine whether HDI is necessary. [2][9]
You should first evaluate conventional routing against the package layout and fabricator's design rules, then consider HDI if the required connections cannot be routed reliably.
Successful BGA PCB design requires more than connecting every solder ball. High-speed signals must maintain reliable transmission, power connections must remain stable, and heat must be dissipated effectively. These factors directly affect the performance and reliability of the finished PCB.
High-speed BGA connections require controlled impedance, continuous reference planes, and properly designed signal transitions. Poor routing can cause signal reflections, crosstalk, and timing errors, particularly in DDR memory and high-speed serial interfaces. [5]
Trace width, dielectric thickness, and copper spacing influence impedance. Differential pairs also require appropriate spacing and skew control. Signal vias should be designed to limit impedance discontinuities while maintaining suitable return-current paths.
For example, AMD's UltraScale Architecture PCB Design User Guide (UG583) describes 50 Ω single-ended transmission lines and 100 Ω differential routing for high-speed transceiver channels. These are interface-specific design targets rather than universal requirements for every BGA signal. [5]
BGA power and ground balls connect to the PCB power-distribution network (PDN) through copper planes and vias. A properly designed PDN delivers the required voltage while limiting voltage drop, switching noise, and transient fluctuations.
Decoupling capacitors help supply short bursts of current when the device switches. Their placement and connection inductance are critical, especially for high-current processors and FPGAs. [5]
For example, AMD UG583 specifies a nominal 1.8 V supply for the Zynq UltraScale+ PS DDR PLL and recommends placing a 1.0 µF 0201 or 10 µF 0402 capacitor near the corresponding BGA via. This illustrates why capacitor placement and supply-specific manufacturer recommendations matter. [5]
Power integrity should be verified against the device's voltage tolerances and expected current demand, using PDN analysis and measurements where necessary.
BGA devices generate heat during operation. Heat flows through the package, solder connections, PCB copper, and surrounding air. Copper planes and thermal vias can improve heat spreading, while heat sinks and airflow may be necessary for higher-power devices.
A preliminary junction-temperature estimate is:
Tj = TA + P × θJA
Here, Tj is junction temperature, TA is ambient temperature, P is dissipated power, and RθJA is the effective junction-to-ambient thermal resistance for the operating conditions.
For example, the Texas Instruments AM62L BGA processor has a published RJA of 22.2 °C/W under specified JEDEC still-air conditions. [6] Assuming an illustrative 2 W power dissipation and 40 °C ambient temperature:
Tj = 40 + (2 × 22.2) = 84.4 °C
This is below the device's 105 °C extended-industrial junction-temperature limit. However, the calculated value is only an initial estimate because the actual PCB construction, enclosure, and cooling conditions affect thermal resistance. TI recommends system-level thermal simulation using worst-case power consumption. [6]
Reliable BGA assembly depends on accurate solder paste printing, component placement, controlled reflow soldering, and properly fabricated PCB features. Following manufacturer guidelines helps maintain consistent solder-joint quality and reduce production defects. [1][4]
Stencil thickness, aperture dimensions, and solder paste characteristics determine how much solder reaches each BGA pad. Poor stencil alignment or inconsistent paste release can affect solder-joint formation. [4]
Analog Devices recommends a 0.100 mm stainless steel stencil and an aperture area ratio greater than 0.66 for the BGA modules covered by its application note. These are manufacturer-specific recommendations, not universal requirements. Solder paste inspection (SPI) helps verify deposit volume, alignment, and consistency before component placement. [4]
BGA placement requires accurate alignment between solder balls and PCB pads. During reflow, controlled preheating, soaking, heating above the solder's liquidus temperature, and cooling help form consistent solder joints. Temperature differences and package warpage must also be considered. [4][7]
Texas Instruments' AN-2029 provides lead-free reflow classification parameters, including 150–200°C preheating for 60–120 seconds and 60–150 seconds above 217°C. These are component qualification parameters, not a universal production recipe. Actual reflow profiles must follow solder paste requirements, device temperature limits, and measurements on the assembled PCB. [7]
Via-in-pad structures require appropriate fabrication to create a reliable soldering surface. Open vias can draw molten solder away from BGA pads, while uneven surfaces can affect solder-joint consistency. [8]
For conventional plated vias placed within solderable BGA pads, filling, planarization, and copper capping are commonly used. IPC-4761 Type VII describes filled and capped vias suitable for this application. Fabrication drawings should specify the required via treatment so the PCB manufacturer can provide a continuous, solderable pad surface [8]
BGA solder joints are hidden beneath the package, making defects difficult to detect visually. Common problems include solder bridging, voiding, open connections, and mechanical damage. Proper inspection and failure analysis help identify their causes and prevent repeated failures. [1][4]
| BGA Failure or Inspection Method | Common Causes or Purpose | Troubleshooting and Prevention |
| Solder Bridging, Voiding, and Open Connections | Excess solder or misalignment can cause bridging. Trapped gases can create voids, while insufficient solder or poor wetting can cause opens. | Use X-ray inspection and electrical testing. Check solder paste volume, placement accuracy, and reflow conditions. |
| Head-in-Pillow Defects, Warpage, and Pad Cratering | Head-in-pillow occurs when solder surfaces fail to join properly, often due to warpage or poor wetting. Pad cratering involves cracks in the PCB laminate beneath solder pads. | Check reflows profiles, package warpage, and mechanical stress. Use advanced inspection or cross-section analysis when necessary. |
| X-Ray Inspection, Electrical Testing, and Failure Analysis | X-ray identifies hidden solder bridges and voids, while electrical tests check connectivity and functionality. Neither method alone detects every defect. | Combine X-ray and electrical testing. Use 3D X-ray, cross-sectioning, or other failure-analysis methods for suspected hidden defects. |
| BGA Rework and Long-Term Reliability Considerations | Improper rework, excessive heating, and mechanical stress can damage solder joints, PCB pads, or packages. | Follow controlled removal and replacement procedures. Inspect repaired joints and verify electrical operation. Apply IPC-7711/21D guidance where applicable. |
Manufacturer design examples demonstrate how BGA pitch, routing density, and fabrication capabilities influence practical PCB layouts. The following AMD and Microchip examples illustrate different approaches to fine-pitch BGA routing.
AMD's UG1099 presents a breakout routing example for the UBVA530 InFO package, which has 530 solder balls at 0.5 mm pitch. Its published layouts illustrate how connections escape through the top PCB layer and two inner signal layers. [2]
The top layer supports one trace between adjacent BGA pads, while the inner layers provide additional paths for signals located deeper within the ball array. AMD specifies approximately 0.27 mm solder-land diameter, 0.08 mm trace width, and 0.08 mm pad-to-trace clearance for this routing arrangement. [2]
These dimensions demonstrate a feasible routing approach, but the tight clearance requires confirmation with the PCB manufacturer. The example illustrates routing geometry rather than guaranteed manufacturing yield.
The original AMD breakout illustrations show the top layer and both inner signal layers.
Microchip's SAMA5D27 routing guidelines demonstrate why dense BGA packages need localized high-density interconnect (HDI) fabrication. The manufacturer recommends via-in-pad structures, blind and buried vias, and fine trace dimensions near the processor. [9]
| Design parameter | Microchip recommendation |
| BGA land diameter | 0.25 mm |
| Local trace width | 0.10 mm |
| Local trace clearance | 0.075 mm |
| Blind/buried via diameter | 0.25 mm |
| Via hole diameter | 0.125 mm |
Beyond approximately 5–10 mm from the package, Microchip permits more relaxed rules, including 0.10 mm trace width and clearance and 0.40 mm through-hole vias with 0.20 mm holes. [9]
This approach limits demanding fabrication features to the area where they are needed. You should confirm these capabilities with the PCB manufacturer before finalizing the layout.
BGA, QFN, QFP, and LGA packages differ in connection density, PCB space requirements, assembly inspection, and routing complexity. The best choice depends on the component's available package options, I/O requirements, electrical performance, and manufacturing capabilities.
| Feature | BGA | QFN | QFP | LGA |
| Connection type | Solder balls underneath | Flat peripheral pads | Leads extending from four sides | Flat contact lands underneath |
| Connection density | High; supports large I/O counts | Low to moderate | Low to moderate | Moderate to high |
| PCB footprint | Compact for high I/O counts | Generally compact | Often larger due to leads | Compact, depending on land arrangement |
| Routing complexity | High for dense ball arrays | Usually moderate | Generally straightforward, but fine-pitch leads add constraints | Moderate to high for dense arrays |
| Assembly inspection | Hidden joints often require X-ray | Hidden underside joints; X-ray may be needed | Visible leads support optical inspection | Hidden joints may require X-ray |
| Rework accessibility | Requires specialized heating and alignment | Requires controlled heating | Leads are more accessible for repair | Requires controlled heating and alignment |
| Thermal performance | Depends on package construction and cooling | Exposed thermal pads can improve heat transfer | Depends on leadframe and thermal design | Depends on package and PCB thermal paths |
| Typical applications | Processors, FPGAs, high-I/O devices | Power-management ICs, sensors, compact controllers | Microcontrollers and industrial electronics | RF devices, power modules, compact high-density assemblies |
Application recommendations: QFN is suitable for compact designs with relatively fewer connections, while QFP is useful when visible solder joints and easier inspection are important. LGA is worth considering for compact modules and high-density applications when the manufacturer supports that package.
Technical References
[1] IPC. “Design and Assembly Process Guidance for Ball Grid Arrays (BGAs).” IPC, 2024. IPC-7095E, August 2024.
[2] Advanced Micro Devices (AMD). “Recommended Design Rules and Strategies for BGA Devices User Guide.” AMD, 2025. UG1099, Version 2.1, October 24, 2025.
[3] Texas Instruments. “DLPC3430 and DLPC3435 Display Controller.” Texas Instruments, 2020. Datasheet DLPS038F, Revision F, November 2020.
[4] Maxim Integrated Products. “Ball Grid Array (BGA) Package Application Notes.” Maxim Integrated, 2014. Application Note 6408 (AN6408).
[5] Advanced Micro Devices (AMD). “UltraScale Architecture PCB Design User Guide.” AMD, 2025. UG583, Version 1.29, December 23, 2025.
[6] Texas Instruments. “AM62Lx Sitara™ Processors.” Texas Instruments, 2025. Datasheet SPRSPA1B, Revision B, November 2025.
[7] Texas Instruments. “AN-2029 Handling and Process Recommendations.” Texas Instruments, 2020. Application Report SNOA550H, Revision H, June 2020.
[8] IPC. “Design Guide for Protection of Printed Board Via Structures.” IPC, 2006. IPC-4761, July 2006.
[9] Microchip Technology. “5.2 HDI PCB Rules.” Microchip Technology, undated online technical documentation. Document DS00005871C, Section 5.2.
[10] IPC. “Thermal Cycling Test Method for Fatigue Life Characterization of Surface Mount Attachments.” IPC, 2022. IPC-9701B, Revision B, February 2022.
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