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SAR ADCs often suit precisely timed, low-latency acquisition. Sigma-delta ADCs combine oversampling, noise shaping, and digital filtering for low-noise measurements. Selection depends on signal bandwidth, usable resolution, filter delay, channel-switching requirements, and the complete analog front end.
Figure 1. An Overview of SAR ADC and Sigma-Delta ADC
A SAR ADC, or Successive Approximation Register ADC, converts an analog input by comparing it against internally generated reference levels. A typical SAR converter contains a sample-and-hold circuit, a comparator, a DAC, and successive-approximation logic.
Once the input has been sampled, the converter determines the digital result one bit at a time, usually starting with the most significant bit. The process resembles a binary search: each comparison determines whether the next trial value should be higher or lower until the final digital code is obtained.
These are general tendencies rather than fixed architectural limits. High-resolution SAR converters and SAR devices with digital filtering are also available.
A sigma-delta ADC, also commonly called a delta-sigma ADC, uses a very different conversion method. Instead of relying on a single sampled value followed by a binary search, it operates a modulator at a rate much higher than the final output data rate.
The modulator includes one or more integrators, a low-resolution quantizer, and a feedback DAC. It produces a high-rate digital stream in which quantization noise is shaped toward higher frequencies. A digital low-pass filter then removes much of this out-of-band noise and decimates the data to produce the final digital output.
This architecture is particularly useful when low noise and fine measurement resolution are required over a limited signal bandwidth.
The last point is device-dependent. Some modern sigma-delta ADCs use low-latency or single-cycle-settling filter modes specifically to improve multiplexed performance.
A SAR ADC conversion can be divided into two main stages: acquisition and conversion.
During acquisition, the analog input charges an internal sampling capacitor. When conversion begins, this sampled voltage is held while the successive-approximation process determines its digital value.
The basic sequence is:
Sample Input → Generate DAC Trial Value → Compare → Adjust Bit → Repeat → Digital Output
For an N-bit SAR ADC, the internal logic typically begins by setting the most significant bit. The DAC generates the corresponding voltage, and the comparator determines whether this value is above or below the sampled input.
The SAR logic then keeps or clears that bit before testing the next one. After the required sequence of comparisons, the final N-bit output represents the sampled voltage.
An important consequence of this architecture is that the sampling event is clearly defined. This makes SAR ADCs useful when the timing of an individual measurement is important, such as in control systems or transient acquisition.
Figure 2. Simplified Working Principle of a SAR ADC
A sigma-delta ADC does not produce its final high-resolution result directly from one comparator sequence. Instead, conversion takes place through several stages:
Analog Input → Sigma-Delta Modulator (with noise shaping) → Digital Filter → Decimation → Digital Output
The modulator samples the signal at a rate that is higher than the final output data rate. Its feedback loop continuously compares the input with a feedback signal and generates a low-resolution digital stream.
The decimation ratio can be defined as R = fMOD / fDR, where fMOD is the modulator sampling rate and fDR is the output data rate. Some datasheets refer to this ratio as OSR (oversampling ratio). At a fixed modulator rate, increasing the decimation ratio lowers the output rate and typically narrows the filter bandwidth; it does not widen the modulator's Nyquist band.
Quantization noise is then shaped so that its density is reduced at lower frequencies and increased toward higher frequencies. The digital low-pass filter suppresses much of this high-frequency noise while retaining the signal band.
Finally, the decimation stage reduces the high-rate modulator data to the desired output data rate. One important distinction follows from this process: the internal modulator sampling rate is not the same as the ADC output data rate.
Figure 3. Simplified First-Order Sigma-Delta ADC
The following table summarizes the general differences between the two architectures.
| Feature | SAR ADC | Sigma-Delta ADC |
| Conversion method | Successive comparison of a sampled input | Oversampling, noise shaping, and digital filtering |
| Sampling behavior | Captures the input at a defined sampling instant | Modulator repeatedly samples the input |
| Typical strength | Low latency and fast signal tracking | High-resolution, low-noise measurement |
| Resolution | Medium to high; high-resolution devices are available | Often used for high and very high resolution |
| Bandwidth | Commonly suited to wider-band signals | Depends strongly on output rate and digital filter |
| Latency | Generally low | Digital filtering introduces latency |
| Noise reduction | Depends on ADC and external signal chain | Noise shaping and digital filtering are inherent |
| Anti-alias filtering | Analog filtering often plays a significant role | Oversampling can relax analog-filter requirements |
| Multiplexing | Often convenient for rapid channel switching | Filter settling must be considered |
| Typical uses | Control, data acquisition, transient measurement | Precision sensors, weighing, temperature measurement |
The table describes common tendencies rather than hard boundaries. Modern devices increasingly overlap in resolution, bandwidth, and integrated features.
ADC resolution specifies the number of digital output levels available. An ideal N-bit converter provides: 2ᴺ possible output codes.
However, nominal resolution alone does not show how much useful measurement information the converter can provide.
Noise, distortion, reference quality, clock performance, PCB layout, and front-end circuitry can all reduce usable performance. For this reason, specifications such as effective number of bits (ENOB), SNR, dynamic range, and input-referred noise often provide more useful information than the nominal bit count alone.
ENOB indicates the resolution an ideal ADC would need in order to match the measured dynamic performance of the converter. It is commonly calculated from SINAD, measured with a full-scale sine-wave input: ENOB = (SINAD − 1.76 dB) / 6.02. For example, a measured SINAD of 98 dB corresponds to an ENOB of about 16 bits, even if the converter’s nominal resolution is higher.
SINAD-derived ENOB describes dynamic performance. For DC sensors, also compare effective resolution, log2(FSR/Vnoise,rms), and noise-free resolution, log2(FSR/Vnoise,pp), at the specified gain, output rate, and filter setting.
Sigma-delta converters are often chosen for measurements that require very low in-band noise. Oversampling and noise shaping reduce quantization-noise density within the signal band, while the digital filter removes a large portion of the higher-frequency content.
SAR ADCs can also provide excellent noise and linearity performance. High-throughput SAR devices can be oversampled and digitally averaged to increase dynamic range. Higher nominal resolution or lower in-band noise does not automatically mean better absolute accuracy. Accuracy also depends on factors such as INL, offset and gain errors, reference accuracy, temperature drift, and the complete signal chain.
SAR converters perform distinct acquisition and conversion operations. Their relatively direct conversion process makes them suitable for applications that need to capture faster-changing signals or take precisely timed samples.
Sigma-delta converters work differently. Their modulator runs faster than the final output data rate, while the digital filter determines how much of the input spectrum appears in the final output.
A precision sigma-delta converter configured for a high oversampling ratio may provide excellent noise performance but a narrow useful bandwidth. Reducing the oversampling ratio can increase bandwidth and output data rate at the expense of noise performance.
There are also wideband sigma-delta converters designed for higher-frequency signals. For this reason, signal bandwidth should be checked against the actual ADC filter response rather than inferred from architecture alone.
Noise performance is one of the main reasons to consider a sigma-delta converter.
Its modulator shapes quantization noise away from the low-frequency signal band. The following digital filter suppresses much of that out-of-band noise. With a sufficiently narrow bandwidth, this process can provide excellent dynamic range for slowly changing sensor signals.
However, the ADC is only one noise source in the system. Amplifier noise, reference noise, resistor thermal noise, sensor noise, power-supply interference, and PCB coupling can all limit the final measurement.
SAR converters do not rely on inherent sigma-delta noise shaping, but they can still achieve high dynamic range through low-noise design, high resolution, oversampling, averaging, and external digital filtering. As a result, noise comparisons should be made at the required signal bandwidth.
Figure 4. Quantization Noise Shaping in a Sigma-Delta ADC
Latency is one of the clearest architectural differences. A traditional SAR ADC produces a conversion result after its acquisition and successive-approximation cycle without the additional group delay of a decimation filter. This makes it attractive for systems that need a prompt response to an input change.
Sigma-delta ADCs pass modulator data through a digital filter before producing the final result. This filter introduces delay.
The amount of latency varies with:
• Filter type
• Filter order
• Output data rate
• Oversampling ratio
• ADC operating mode
This distinction matters especially after a large input step or multiplexer channel change. The first output word after a change is not always a fully settled representation of the new input.
For an unmodified sinc³ filter at 1,000 SPS, full step settling is approximately 3/fDR=3 ms. Scanning four channels with one settled reading per visit gives approximately 83 readings/s/channel before analog-settling and interface overhead.
A high-performance ADC cannot achieve its specified performance unless the analog source can drive its input correctly.
Many SAR ADCs use a switched-capacitor input network. During acquisition, an internal capacitor must charge to the input voltage. The driver therefore needs enough bandwidth and settling capability to bring the ADC input to the required accuracy before acquisition ends.
Source impedance, acquisition time, ADC input capacitance, and any RC network placed between the amplifier and converter all influence settling.
An RC network is often placed near a SAR ADC input to reduce wideband noise and help isolate the amplifier from the switched-capacitor load. However, excessive resistance or capacitance can prevent the input from settling in time.
Sigma-delta ADCs also require proper input-drive design. Some devices include input buffers or PGAs, while unbuffered devices may expose the source more directly to the modulator input.
For either architecture, the device datasheet should be used to verify input impedance and settling requirements.
All sampled-data systems must address aliasing.
For many SAR ADC applications, the analog front end includes an anti-aliasing low-pass filter that attenuates signals and noise above the desired input band before they reach the converter.
Sigma-delta ADCs usually relax this requirement because the modulator samples much faster than the final signal bandwidth and the integrated digital filter strongly attenuates frequencies outside its passband.
However, digital filtering cannot prevent aliasing that occurs at the modulator input. Out-of-band interference near the modulator sampling frequency and its alias regions can still fold into the signal band. Therefore, an external analog filter is still required when such interference is present. Sigma-delta ADCs can relax analog anti-aliasing requirements, but they do not automatically eliminate them.
Multiplexing introduces another important design difference.
With a SAR ADC, a new channel can generally be sampled once the multiplexer, driver, and ADC input have settled.
However, a large voltage step between channels may require the multiplexer, amplifier, RC network, and sampling capacitor to settle within a short acquisition window.
Sigma-delta ADCs add another factor: digital-filter settling.
When the input channel changes, the filter may still contain information from the previous channel. Depending on the filter architecture, additional output periods may be required before the new result is fully settled.
Some modern sigma-delta ADCs reduce this delay with low-latency or single-cycle-settling filter modes.
Power consumption should be compared at the device and system level rather than treated as a fixed advantage of either architecture.
Many SAR ADCs work well in duty-cycled systems and can provide good power efficiency at lower sampling rates.
Sigma-delta ADCs may integrate functions such as:
• Programmable-gain amplifiers
• Input multiplexers
• Voltage references
• Oscillators
• Sensor excitation current sources
• 50 Hz and 60 Hz rejection filters
These features can reduce external component count and analog-front-end complexity.
Modern SAR ADCs can also include references, buffers, filters, and sequencers, so total signal-chain power and component count are generally more useful design metrics than ADC core power alone.
| ADC Type | Typical Application | Why It Fits |
| SAR ADC | Industrial control and motor drives | Low latency and predictable sampling help support fast feedback and control loops |
| SAR ADC | Multichannel data acquisition | High throughput and relatively fast channel switching suit systems that scan multiple inputs |
| SAR ADC | Transient measurement | A clearly defined sampling instant helps capture pulses, steps, and other rapidly changing signals |
| SAR ADC | Power and battery monitoring | Provides a useful balance of speed, resolution, and power efficiency for voltage and current measurement |
| SAR ADC | Test and measurement | Precision devices can combine good DC performance with the ability to track dynamic signals |
| Sigma-Delta ADC | Temperature measurement | High resolution, low noise, and digital filtering suit slow signals from RTDs and thermocouples |
| Sigma-Delta ADC | Load cells and weigh scales | Low-noise measurement and integrated PGAs are useful for small differential bridge signals |
| Sigma-Delta ADC | Pressure and precision sensors | Noise shaping and narrow digital-filter bandwidth support low-level, low-frequency sensor signals |
| Sigma-Delta ADC | Precision DC measurement | High dynamic range is useful in instrumentation and other precision low-frequency measurements |
| Sigma-Delta ADC | Audio and vibration measurement | Continuous oversampling and digital filtering suit signals measured over a defined frequency band |
Choosing an ADC should start with the measurement requirements rather than with a preferred architecture.
Step 1: Determine the Signal Bandwidth
First identify how quickly the input can change. Questions to consider include:
• Is the signal essentially DC?
• Is it a slowly changing sensor output?
• Does it contain audio- or vibration-frequency content?
• Must the system capture fast transients?
• Is the ADC part of a closed feedback loop?
Slow sensor measurements often leave room for aggressive digital filtering. Fast-changing signals and control loops usually place more emphasis on bandwidth and latency.
Verify passband flatness,-3 dB bandwidth, and stopband for the selected filter. Output data rate divided by two is a Nyquist limit, not a guarantee of a usable bandwidth.
Step 2: Define the Resolution, Noise, and Accuracy Requirements
Do not select a converter based only on nominal resolution. Check specifications such as:
• Input-referred noise
• SNR
• ENOB
• Dynamic range
• INL
• Offset and gain errors
• Temperature drift
For low-frequency signals, compare noise over the actual measurement bandwidth.
Step 3: Check the Latency Requirement
Ask how quickly the digital output must respond when the analog input changes.
If the converter is used in a fast control loop, event capture system, or transient measurement path, low conversion latency may favor a SAR architecture.
If the signal changes slowly and the system can tolerate digital-filter delay, sigma-delta conversion may provide stronger in-band noise performance.
Step 4: Consider Multiplexing and Channel Count
For a SAR design, determine whether the multiplexer and ADC driver can settle within the available acquisition time.
For a sigma-delta converter, check:
• Filter settling after a channel change
• Single-cycle-settling capability
• Effective per-channel data rate
• Whether each channel can use independent gain or filter settings
The maximum ADC output data rate may not equal the maximum rate of fully settled readings in a multiplexed system.
Step 5: Evaluate the Complete Signal Chain
Finally, compare what is required around the converter. Consider:
• Input driver
• PGA
• Voltage reference
• Multiplexer
• Anti-aliasing filter
• Digital filtering
• Clock
• Power consumption
• Digital interface
• PCB area
• Component cost
The best ADC is the one that meets the complete signal-chain requirements, not simply the one with the highest bit count or sampling rate.
SAR and sigma-delta ADCs use different conversion techniques, leading to different trade-offs in bandwidth, latency, noise, and system design.
SAR ADCs are often preferred for low-latency and precisely timed measurements, while sigma-delta ADCs are well suited to high-resolution, low-noise applications. The final choice should depend on the complete signal-chain requirements rather than the ADC architecture alone.
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