A digital signal processor (DSP) is a specialized processor designed to perform mathematical operations on digital signals efficiently. It is commonly used for audio filtering, noise reduction, communications, and real-time sensor processing. Digital signal processing can also run on microcontrollers, CPUs, and FPGAs without a dedicated DSP chip. A dedicated DSP is useful when applications require sustained processing throughput, predictable timing, or low power consumption. For simpler tasks, a microcontroller or general-purpose processor may provide sufficient performance at a lower system cost.

Figure 1. Analog Devices EV-21569-SOM Development Board Featuring the ADSP-21569 SHARC+ DSP
A digital signal processor (DSP) works by performing mathematical operations on digital signals. For analog inputs, such as audio or sensor signals, an analog-to-digital converter (ADC) converts the signal into digital samples. The DSP then processes these samples using algorithms to filter noise, adjust frequencies, or extract useful information. If an analog output is required, a digital-to-analog converter (DAC) converts the processed data back into an analog signal. [4]
DSPs use specialized hardware, including multiply-accumulate (MAC) units, to perform repeated calculations efficiently. A multiply-accumulate operation multiplies two values and adds the result to an accumulator. Digital filters repeatedly use this operation to combine samples with filter coefficients. For real-time processing, the DSP must complete each processing task or sample block before its deadline to prevent delays or data loss. This makes DSPs suitable for continuous signal processing in audio systems, industrial control, and communications.
Digital signal processor (DSP) performance depends on processing speed, numerical precision, memory access, latency, and power consumption. These specifications determine how efficiently a DSP handles demanding tasks such as audio filtering, signal analysis, and real-time control. A higher clock speed alone does not guarantee better performance because processor architecture, memory bandwidth, and algorithm efficiency also affect results.
Clock speed, measured in megahertz (MHz) or gigahertz (GHz), indicates how many clock cycles a DSP completes per second. Multiply-accumulate (MAC) throughput measures how quickly it performs repeated multiplication and addition operations used in digital filters and signal-processing algorithms. [6]
Processing capacity also depends on the number of execution units, parallel processing capabilities, and memory access speed. Metrics such as MIPS and FLOPS describe different aspects of performance but do not directly indicate how fast an application will run. Actual algorithm benchmarks provide a more reliable comparison than clock speed alone.
Fixed-point DSPs represent numbers using scaled integers. They can provide efficient processing with relatively low memory requirements, making them useful in cost-sensitive embedded systems. However, algorithms must carefully manage numerical scaling, overflow, and quantization errors.
Floating-point DSPs represent numbers using a significand and exponent, allowing a much wider numerical range. This simplifies calculations involving very large or small values and reduces the need for manual scaling. Floating-point processing is useful for complex audio, imaging, and scientific applications, although the best choice depends on the required precision, hardware, cost, and power consumption.
Memory capacity determines how much program code, signal data, filter coefficients, and temporary processing information a DSP can store. Fast internal memory and cache reduce access delays, while memory bandwidth determines how quickly data can move between the processor and storage.
Direct memory access (DMA) allows supported peripherals and memory regions to transfer data without requiring the processor to handle every transfer. This can reduce CPU workload and improve processing efficiency. However, limited memory bandwidth or competing transfers can still reduce performance. [3]
Processing latency is the delay between receiving input data and producing the corresponding processed output. It depends on algorithm complexity, buffering, memory access, and system scheduling. Low latency is especially important in real-time audio, communications, and control systems.
Power consumption depends on operating voltage, clock frequency, processing activity, and enabled peripherals. [7] Higher processing demands can increase energy use and heat generation. For battery-powered or thermally constrained devices, you should compare measured power consumption under realistic workloads rather than relying only on maximum processing specifications.
Real-time audio filtering requires a digital signal processor (DSP) to process incoming audio samples without interrupting playback. Consider a stereo audio system operating at a 48 kHz sample rate, using a 128-tap finite impulse response (FIR) filter per channel and a block of 64 samples per channel, equivalent to 64 stereo frames. This example shows how to estimate processing workload, buffering delay, and the performance required for continuous operation.
An FIR filter applies multiple coefficients to each incoming sample using multiply-accumulate (MAC) operations. A straightforward 128-tap FIR filter requires approximately 128 MAC operations per output sample per channel. [5,6]
For a stereo system running at 48,000 samples per second per channel:
MAC operations per second = Sample rate × Filter taps × Channels
= 48,000 × 128 × 2 = 12.288 million MAC operations per second
This is the theoretical filtering workload before implementation optimizations and processing overhead. The actual execution time depends on the DSP architecture, memory access, and algorithm implementation.
Audio systems commonly process samples in blocks to reduce processing overhead. [4,6] With 64 samples per channel (64 stereo frames) at 48 kHz, the block duration is:
Block duration = Samples per channel ÷ Sample rate
= 64 ÷ 48,000 = 1.33 milliseconds (ms)
The DSP receives a new block of 64 stereo frames every 1.33 ms and must complete the required processing before the next deadline. This block duration is not the total audio latency. Additional delays can come from input/output buffering, converters, and the filter itself. For example, a 128-tap linear-phase FIR filter has a group delay of approximately 1.32 ms.
The example requires approximately 12.288 million MAC operations per second, or 16,384 MAC operations per block of 64 stereo frames (64 samples per channel). However, the processor must also handle memory transfers, interrupts, and other system tasks.
To determine whether a DSP is suitable, measure the worst-case processing time of the complete audio workload on the target hardware. Processing must consistently finish within the 1.33 ms block deadline, with sufficient time remaining for other operations and timing variations. If the deadline is missed, audio dropouts or buffer overruns may occur. A processor that meets the MAC requirement but fails these timing tests is unsuitable for the intended real-time application.
Digital signal processors (DSPs) are widely used for real-time signal processing in various applications, including:
• Audio Processing: Reduce noise, cancel echoes, and improve sound quality in headphones, speakers, and audio systems.
• Industrial Control: Process sensor data and control motor speed, position, and current in automated equipment.
• Radar and Wireless Communications: Analyze radar signals and support filtering, modulation, and signal detection.
• Medical Equipment: Process ultrasound signals and improve medical imaging and monitoring.
• Image and Video Processing: Enhance images, reduce noise, and support video compression in cameras and surveillance systems.
• Power Electronics: Process voltage and current signals to control solar inverters, UPS systems, and power converters.
Gamechanger Audio developed the Bigsby Pedal using the Analog Devices ADSP-21569 SHARC+ digital signal processor. The pedal digitally reproduces guitar pitch-bending effects without requiring a mechanical tremolo arm. The implementation is documented by Kokaly-Bannourah and Swahn (2024) in an Analog Devices technical article. [8]
The main challenge was changing the pitch of multiple guitar notes simultaneously while preserving their natural sound and responding quickly to foot-pedal movements. The algorithm needed to minimize audible artifacts and processing delays during live performance. [8]
Unlike a conventional single-note pitch shifter, the Bigsby Pedal processes complex musical signals containing multiple notes. The manufacturer documents upward and downward pitch shifting up to 12 semitones in each direction. [9] This is a supported product capability, not a measured accuracy result.
The design uses the ADSP-21569 SHARC+ processor, which provides: [2,5]
• Clock speed: Up to 1 GHz, depending on the processor variant.
• L1 memory: 640 KB of on-chip SRAM.
• L2 memory: 1,024 KB of on-chip SRAM.
• Processing: Fixed-point and floating-point capabilities, with FIR/IIR hardware accelerators.
The complete pedal specifies 24-bit A/D and D/A conversion at 48 kHz. [9]
The DSP’s processing architecture and internal memory support the demanding pitch-shifting algorithm. Its audio interfaces also help transfer signal data efficiently. However, the published case study does not identify the processor’s actual operating frequency, memory utilization, or processing workload during pedal operation.
Digital signal processors (DSPs), microcontrollers, CPUs, FPGAs, and GPUs can all process digital signals, but they differ in processing architecture, memory, hardware acceleration, and application requirements. The following table compares specific devices and platforms using manufacturer-published specifications.
| Specification | DSP | Microcontroller | CPU | FPGA | GPU |
| Example Device or Platform | ADI ADSP-21569 [2] | STM32H743ZI [10] | Broadcom BCM2712 [11] | AMD XC7A100T [12,13] | NVIDIA Jetson Orin Nano Super Developer Kit [14] |
| Architecture | SHARC+ DSP | Arm Cortex-M7 | Quad-core Arm Cortex-A76 | Artix-7 programmable logic | NVIDIA Ampere |
| Maximum Clock Speed | 1 GHz | 480 MHz | 2.4 GHz | Configuration-dependent | 1,020 MHz GPU |
| Processing Resources | Single DSP core with FIR/IIR accelerators | DSP instructions and FPU | 4 CPU cores | 240 DSP48E1 slices | 1,024 CUDA cores, 32 Tensor Cores |
| Numerical Processing | Fixed point and floating-point | Integer and floating-point | Integer and floating-point | Configurable fixed-point and floating-point implementations | Integer and floating-point |
| Memory Resources | 640 KB L1, 1,024 KB L2 SRAM | Up to 1 MB RAM, 2 MB Flash | 512 KB L2 per core, 2 MB shared L3; external RAM | 4,860 Kb block RAM | 8 GB LPDDR5 system memory |
| Memory Bandwidth | Architecture-dependent | Architecture-dependent | System-dependent | Design-dependent | 102 GB/s |
| Primary Strength | Dedicated signal-processing acceleration | Integrated control and signal processing | General-purpose software processing | Custom parallel processing pipelines | Massively parallel computation |
| Typical Applications | Audio effects, digital filtering | Sensors, motor control | Software signal analysis | Radar pipelines, high-speed filtering | Image processing, computer vision |
The devices have different architectures and memory systems. Clock frequencies, core counts, and processing resources are not directly comparable measures of DSP performance. Actual performance depends on the workload, implementation, and test conditions. Jetson performance specifications depend on the selected power mode.
The following five established DSP models from Texas Instruments and Analog Devices demonstrate different processing capabilities, memory configurations, and application requirements.

Figure 2. Texas Instruments TMS320C6748 DSP Development Board
The TMS320C6748 is a fixed-point and floating-point DSP based on Texas Instruments' C674x very long instruction word (VLIW) architecture. It operates at clock speeds up to 456 MHz and supports efficient mathematical processing through parallel execution units. The processor also includes DMA, audio interfaces, and communication peripherals. [1] It is suitable for embedded audio processing, industrial control, digital filtering, and signal analysis applications.

Figure 3. EV-21569-EZKIT Evaluation System with EV-21569-SOM and EV-SOMCRR-EZKIT.
The ADSP-21569 is a high-performance SHARC+ DSP designed for applications requiring intensive real-time signal processing. It supports clock speeds up to 1 GHz, 640 KB of L1 memory, and 1,024 KB of L2 SRAM. Dedicated FIR and IIR accelerators help process digital filters efficiently. [2] Its floating-point capabilities and audio interfaces make it suitable for professional audio equipment, automotive sound systems, noise cancellation, and multichannel audio processing.

Figure 4. Tronlong SOM-TL6678F Module Featuring the TI TMS320C6678 DSP and Xilinx Kintex-7 FPGA
The TMS320C6678 is a multicore DSP based on Texas Instruments' KeyStone architecture. It integrates eight C66x DSP cores, with currently listed variants operating at up to 1.25 GHz per core. The processor supports fixed-point and floating-point operations, DDR3 memory, PCIe, and high-speed communication interfaces. [15] Its multicore architecture makes it suitable for computationally demanding applications such as telecommunications, medical imaging, high-performance signal analysis, and industrial automation.

Figure 5. Analog Devices ADSP-21489 SHARC DSP EZ-KIT Lite Evaluation Board
The ADSP-21489 is a SHARC DSP designed for high-performance audio and embedded signal processing. It operates at up to 450 MHz and supports fixed-point and floating-point calculations. The processor includes hardware accelerators for FIR filtering, IIR filtering, and fast Fourier transforms (FFT), along with 5 Mbits of on-chip RAM. [16] These features make it suitable for digital audio effects, automotive audio systems, multichannel sound processing, and industrial applications.

Figure 6. Texas Instruments TMS320C5535 eZdsp Evaluation Board
The TMS320C5535 is a low-power, 16-bit fixed-point DSP based on Texas Instruments' C55x architecture. It operates at up to 100 MHz and includes dual multiply-accumulate units, a hardware FFT accelerator, and integrated peripherals such as USB and a 10-bit SAR ADC. [17] Audio applications typically use an external audio codec connected through I²S. [18] Its power-efficient architecture makes it suitable for portable audio devices, voice processing, battery-powered equipment, and embedded signal-processing systems.
Consider these key factors when selecting a digital signal processor (DSP):
• Signal Requirements: Check signal bandwidth, sampling rate, and channel count to determine the processing workload.
• Processor Performance: Evaluate processing speed, memory, numerical precision, and latency to ensure the DSP meets real-time requirements.
• Hardware Compatibility: Verify that the DSP supports the required audio, communication, and peripheral interfaces.
• Development Support: Check available software libraries, compilers, debugging tools, and development boards.
• Cost and Availability: Compare total system cost, power consumption, manufacturer support, and long-term product availability.
Technical References:
[1] Texas Instruments. “TMS320C6748 Fixed- and Floating-Point DSP.” Texas Instruments, 2017. Datasheet SPRS590G, Revision G.
[2] Analog Devices. “SHARC+ Single Core High-Performance DSP (Up to 1 GHz): ADSP-21562/21563/21565/21566/21567/21569.” Analog Devices, 2023. Datasheet, Revision D.
[3] Texas Instruments. “TMS320C6748 DSP Technical Reference Manual.” Texas Instruments, 2016. Document SPRUH79C, Revision C.
[4] Skolnick, David, and Noam Levine. “Digital Signal Processing 101—An Introductory Course in DSP System Design: Part 1.” Analog Devices, 1997. Analog Dialogue, Vol. 31, No. 1.
[5] Nayak, Sanket, and Mitesh Moonat. “Using ADSP-2156x High-Performance FIR/IIR Accelerators.” Analog Devices, 2019. Engineer-to-Engineer Note EE-408, Revision 2.
[6] Moonat, Mitesh, and Sanket Nayak. “Leveraging the On-Chip FIR and IIR Hardware Accelerators on a Digital Signal Processor.” Analog Devices, 2020. Analog Dialogue, Vol. 54, No. 2.
[7] Ragagopal, Prasanth. “Estimating Power for ADSP-2156x SHARC+ Processors.” Analog Devices, 2021. Engineer-to-Engineer Note EE-414, Revision 2.
[8] Kokaly-Bannourah, Maikel, and Martin Swahn. “Gamechanger Audio Bigsby® Pitch-Shifting Pedal with State-of-the-Art Audio Digital Signal Processing.” Analog Devices, 2024. Technical Article.
[9] Gamechanger Audio. “BIGSBY PEDAL Support.” Gamechanger Audio, n.d. Product Technical Specifications and Support Documentation. Accessed October 12, 2026.
[10] STMicroelectronics. “STM32H742xI/G STM32H743xI/G: 32-bit Arm® Cortex®-M7 480MHz MCUs, up to 2MB flash, up to 1MB RAM, 46 com. and analog interfaces.” STMicroelectronics, 2026. Datasheet DS12110, Revision 11.
[11] Raspberry Pi Ltd. “Processors.” Raspberry Pi Documentation, n.d. BCM2712 Processor Specifications. Accessed October 12, 2026.
[12] Xilinx. “7 Series FPGAs Data Sheet: Overview.” Xilinx (now AMD), 2020. Document DS180, Revision 2.6.1.
[13] Xilinx. “7 Series DSP48E1 Slice User Guide.” Xilinx (now AMD), 2018. Document UG479, Revision 1.10.
[14] Sheshadri, Suhas Hariharapura, Leela Subramaniam Karumbunathan, and Dustin Franklin. “NVIDIA Jetson Orin Nano Developer Kit Gets a ‘Super’ Boost.” NVIDIA, 2024. NVIDIA Technical Blog.