Logic gates are the basic building blocks of digital circuits because they allow electronic systems to process binary signals, make decisions, and control other parts of a system. Although their Boolean functions are simple, real logic design involves more than knowing symbols and truth tables. You also need to understand voltage levels, logic families, propagation delay, output drive, loading, and power. This article explains the main logic gates, shows how truth tables and Boolean expressions are turned into working circuits, compares NAND and NOR implementations, examines a practical 3.3 V-to-5 V logic interface, and discusses when discrete gates, MCUs, CPLDs, or FPGAs are the better choice.

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Figure 1. Common Distinctive-Shape Symbols for AND, NAND, OR, NOR, NOT, XOR, and XNOR Gates.

How Logic Gates Work in Digital Circuits

A logic gate is a digital circuit that applies a Boolean function to one or more input signals and produces a corresponding output. Digital logic uses two abstract states, normally represented as 0 and 1, or LOW and HIGH. These states allow electronic circuits to make decisions, process binary information, and control other parts of a digital system.

Logical 0 and 1 should not be treated as exact voltage values. In physical hardware, they are represented by voltage ranges that the device recognizes as LOW or HIGH. The acceptable input and output levels depend on the logic device, supply voltage, and logic family. This means a logic 1 is not necessarily exactly equal to the supply voltage, and a logic 0 is not necessarily exactly 0 V. The specific voltage limits and compatibility requirements are discussed later in the article.

When several gates are connected, the output of one gate can become the input of another. In combinational logic, the resulting output is determined by the present combination of input states. This basic input-processing-output relationship is the foundation for larger digital circuits, while the following sections explain how individual gate functions are represented, combined, and implemented in practical hardware.

Logic Gate Symbols, Truth Tables, and Boolean Expressions

The table below uses A and B for the inputs and Y for the output throughout. AND, OR, NAND, NOR, XOR, and XNOR are shown as two-input gates, while NOT uses only input A.

Logic Gate Truth Table

From a Truth Table to a Working Logic Circuit

A truth table becomes more useful when it is connected to a practical control requirement. Consider a conceptual machine-enable example. The machine should receive a RUN command only when the START command is active, the GUARD is closed, and no FAULT is present.

For this example, define the signals as follows: START = 1 when a start command is active, GUARD = 1 when the guard is closed, and FAULT = 1 when a fault is detected. The required output is RUN.

This example demonstrates Boolean logic only. A real machine safety function must use an appropriately designed and validated safety-related control system. This warning is important because ISO 13849-1:2023 covers the design and integration of safety-related parts of control systems that perform safety functions, rather than a simple ordinary gate example used only for illustration. [7]

Define the Requirement

The machine can run only when all three required conditions are satisfied:

• START = 1

• GUARD = 1

• FAULT = 0

Because the fault condition must be inactive, the FAULT signal must first be inverted before it is combined with the other conditions.

Build the Truth Table

The truth table lists every possible combination of the three input signals.

Only one input combination produces RUN = 1: START and GUARD are both active while FAULT is inactive.

Derive the Boolean Expression

The required output can therefore be written as:

RUN = START · GUARD · ¬FAULT

Here, ¬FAULT represents the inverted fault signal. The dots represent AND operations. This expression states that all three conditions must evaluate to logic 1 before RUN becomes logic 1.

Convert It into Gates

The Boolean expression can now be implemented with logic gates. First, the FAULT signal passes through a NOT gate to produce ¬FAULT. Then START, GUARD, and ¬FAULT feed a three-input AND gate. The output of that gate becomes RUN.

Conceptual gate-circuit diagram:

Figure 2. Machine Enable Logic Circuit Using START, GUARD, and Inverted FAULT Inputs

This completes the design flow:

Requirement → Truth Table → Boolean Expression → Gate Circuit

This method can be applied to many digital-control problems. Start by defining what each input state means, determine which combinations should activate the output, write the corresponding Boolean expression, and then implement that expression with suitable gates.

NAND and NOR as Universal Gates

Conventional Gate Implementation

Using conventional gates, first define the two intermediate terms separately:

P = AB

Q = C

The final output is:

F = P + Q

Therefore,

F = AB + C

This implementation requires one AND gate, one NOT gate, and one OR gate. The longest input-to-output path passes through two gate stages, so the maximum logic depth is two.

NAND-Only Implementation

Starting with:

F = AB + C

Apply De Morgan’s law:

F = AB · C

The first NAND gate produces:

P = AB

The second NAND gate produces:

F = PC

Substituting P:

F = AB · C

Therefore,

F = AB + C

Only two NAND gates are required, with a maximum logic depth of two gate stages.

NOR-Only Implementation

The same Boolean function can be rewritten in product-of-sums form:

F = (A + C) (B + C)

First, use a NOR gate with both inputs connected to C to generate its complement:

Q = C + C

Therefore,

Q = C

The next two NOR gates produce:

P = A + Q

R = B + Q

The final NOR gate combines these two outputs:

F = P + R

Substituting P and R:

F = A + Q + B + Q

Applying De Morgan’s law:

F = (A + Q) (B + Q)

Since Q = C:

F = (A + C) (B + C)

This implementation requires four NOR gates and has a maximum logic depth of three gate stages.

All complements are grouped so the overbar covers the complete intended term, such as AB, A + C, and P + R, rather than only the final variable or symbol.

Logic Gate Parameters

Logic-gate selection requires more than checking the Boolean function. The electrical parameters determine whether the gate can interface correctly with other devices, meet timing requirements, drive the intended load, and operate reliably under the expected power and temperature conditions.

Logic-Level and Loading Parameters

Timing, Power, and Environmental Parameters

CMOS Logic Families and TTL Compatibility

CMOS logic families differ in supply-voltage range, input thresholds, switching performance, power characteristics, and intended use. TI’s Logic Guide SDYU001AC, Rev. AC, November 2025, provides family-level comparisons for HC, HCT, AHC, AHCT, LVC, AUP, and AUC. [1]

The TI Family Speed Class values are broad family comparisons, not guaranteed maximum operating frequencies for every device. Actual timing depends on the specific part, supply voltage, load, temperature, and datasheet test conditions. Input compatibility is also important. HCT and AHCT use TTL-compatible input thresholds at 5 V, while HC, AHC, LVC, AUP, and AUC use CMOS-level input requirements appropriate to their operating ranges. For LVC, the standard family is specified at 1.65–3.6 V, while LVCxG devices extend operation to 5.5 V. [1]

Design Example: 3.3 V MCU Driving 5 V Logic

A 3.3 V microcontroller output is not automatically compatible with every 5 V logic input. Compatibility depends on the MCU’s guaranteed output levels and the receiver’s specified input thresholds, not simply on the nominal supply voltages.

TI’s 5 V logic switching-standard comparison provides representative input thresholds for standard CMOS and TTL-compatible CMOS. These are representative switching standards rather than universal limits for every IC. Always check the selected device’s datasheet. [1]

Figure 3. 3.3 V MCU Interface to Standard and TTL-Compatible 5 V Logic

For a standard 5 V CMOS input, a nominal 3.3 V MCU output may fall below the required HIGH threshold. Therefore, the connection is not guaranteed simply because the MCU output is described as 3.3 V. The HIGH-level compatibility requirement is: [1]

V_{OH(min, MCU)} ≥ V_{IH(min, receiver)}

TTL-compatible CMOS families such as HCT use lower input thresholds. For example, the SN74HCT00 specifies TTL-compatible input thresholds over its recommended 4.5–5.5 V supply range. A 3.3 V MCU can therefore often drive this type of input, provided the MCU’s guaranteed output levels meet the receiver requirements. [6]

Both HIGH and LOW states must be verified:

V_{OH(min, MCU)} ≥ V_{IH(min, receiver)}

and

V_{OL(max, MCU)} ≥ V_{IL(max, receiver)}

In Figure 3, the MCU output is labeled:

3.3V nominal output; verify V_OHat the required load.

The connection is valid only when both equations are satisfied.

This example shows why nominal supply voltage alone does not determine logic compatibility. The source’s guaranteed HIGH and LOW output levels must be compared with the receiver’s specified input thresholds.

Logic Gates vs. MCU, CPLD, and FPGA Implementation

Likewise, no platform is universally faster, lower power, or simpler. The appropriate choice depends on the required logic complexity, latency, parallelism, power target, update requirements, available development tools, cost, and device resources.

Technical References

[1] Texas Instruments. Logic Guide, Rev. AC, SDYU001AC, revised November 2025.

[2] Nolan, S. M., Soltero, J. M., and Rao, S. Understanding and Interpreting Standard-Logic Data Sheets, Rev. C, Texas Instruments, SZZA036C, revised December 2015.

[3] Texas Instruments. CMOS Power Consumption and Cpd Calculation, Rev. B, SCAA035B, June 1997.

[4] Texas Instruments. Implications of Slow or Floating CMOS Inputs, Rev. E, SCBA004E, revised July 2021.

[5] Texas Instruments. SN74LVC1G00 Single 2-Input Positive-NAND Gate Datasheet, Rev. AC, August 2026.

[6] Texas Instruments. SNx4HCT00 Quadruple 2-Input Positive-NAND Gates Datasheet, Rev. F, revised October 2022.

[7] International Organization for Standardization. ISO 13849-1:2023, Safety of Machinery - Safety-Related Parts of Control Systems - Part 1: General Principles for Design, 4th ed., April 2023.