The STM32F103C6T6 is a low-density STM32F1 microcontroller built around a 72 MHz Arm Cortex-M3 core. Its LQFP-48 configuration provides 32 KB of Flash, 10 KB of SRAM, 37 GPIOs, 10 external channels shared by two 12-bit ADCs, one advanced-control timer, two general-purpose timers, seven DMA channels, and USB, CAN, USART, SPI, and I²C interfaces. It is suitable for compact sensor acquisition, PWM and motor control, and embedded communication systems. ST lists the STM32F103C6 family as active and identifies STM32F103C6T6A and STM32F103C6T6ATR as current LQFP-48 order codes.

Catalog

Figure 1. STM32F103C6T6

STM32F103C6T6 Pinout Functions

The STM32F103C6T6 uses a 48-pin LQFP package and provides 37 GPIO pins. Many GPIO pins support alternate functions, including ADC inputs, PWM outputs, USART, SPI, I²C, CAN, USB, clock signals, and debugging. These functions are selected by configuring the relevant peripheral, the GPIO mode, and the AFIO registers when remapping is required. Functions assigned to the same physical pin cannot be used at the same time.

Figure 2. LQFP48 Pinout for STM32F103x4/x6 Low-Density Devices

Architecture and Working Principles

STM32F103C6T6 Architecture

The STM32F103C6T6 belongs to the STM32F103x4/x6 low-density performance-line family and uses a 32-bit Arm Cortex-M3 core operating at up to 72 MHz. Figure 3 is the official family-level block diagram; therefore, some I/O and ADC counts shown in the diagram represent the maximum available on larger package variants rather than the exact resources of the C6 LQFP48 device.

Figure 3. Official STM32F103x4/x6 Family-Level Block Diagram

The internal bus architecture links the processor, memories, DMA controller, and peripheral buses. The AHB domain connects the Cortex-M3 core, Flash memory, SRAM, and seven-channel DMA controller and can operate at up to 72 MHz. Peripheral functions are divided between the two APB domains. APB1 is limited to 36 MHz, while APB2 can operate at up to 72 MHz. The DMA controller can transfer data between supported peripherals and SRAM without requiring the CPU to move every data item, reducing processor workload during repetitive data transfers.

STM32F103C6T6 Working Principle

Figure 4. Simplified STM32F103C6T6 Working Flow Showing Startup, Data Processing, Interrupts, DMA, Output Control, and Low-Power Modes

The STM32F103C6T6 starts after power-on or reset, selects the boot source, and initially uses the 8 MHz HSI clock. Firmware then configures the system clock, GPIOs, and required peripherals.

During operation, the Cortex-M3 processes input data and controls outputs. DMA can transfer data between supported peripherals and SRAM with less CPU involvement, while the NVIC handles and prioritizes interrupts.

When idle, the device can enter Sleep, Stop, or Standby mode. After Stop-mode wake-up, firmware may need to restore the PLL and selected system clock. Wake-up from Standby causes a reset-style restart.

Technical Specifications

Note: ST currently lists the STM32F103C6 family as active and identifies STM32F103C6T6A and STM32F103C6T6ATR as current LQFP-48 order codes. For legacy STM32F103C6 devices with a blank internal code after temperature suffix 6 or 7, including STM32F103C6T6, DS5936 Rev. 7, Figure 3, note 1 directs readers to DS5319 for electrical characteristics. Device memory, peripheral counts, and pinout remain defined by DS5936.

Project Setup, Programming, and Debugging

The STM32F103C6T6 is normally programmed and debugged through its Serial Wire Debug (SWD) interface using an ST-LINK probe. Standalone STM32CubeMX is used to configure pins, clocks, and peripherals and generate the project, while STM32CubeIDE provides code editing, building, Flash programming, and debugging.

The menu paths in this section describe the Eclipse/CDT-based STM32CubeIDE 2.2.0, released on June 30, 2026. They do not apply to the separate STM32CubeIDE for VS Code product.

ST-LINK SWD Connections

Use a regulated 3.3 V target supply. On a genuine ST-LINK/V2, VAPP/VTref senses the target voltage rather than supplying power to the MCU. Keep BOOT0 low for normal startup from user Flash memory; raising BOOT0 is not required for ST-LINK programming.

Programming Procedure

• Open standalone STM32CubeMX and select the exact STM32F103C6Tx device. Configure the clock, GPIOs, peripherals, and Serial Wire debugging under System Core → SYS.

• Open Project Manager, select STM32CubeIDE under Toolchain/IDE, and generate the code. STM32CubeMX documents the Toolchain/IDE selection as part of the project-generation configuration.

• In Eclipse-based STM32CubeIDE, select File → Import → Import STM32 Project → STM32CubeMX/STM32CubeIDE Project. Select the generated project and complete the import.

• Add the application code inside the designated USER CODE sections, build the project, connect the ST-LINK probe through SWD, and start the debugger. Use breakpoints, stepping, register views, and variable monitoring to verify operation.

For reproducible development and testing, record the STM32CubeIDE version, STM32CubeMX version, STM32CubeF1 firmware package version, compiler and toolchain version, ST-LINK firmware version, and project version used for each build.

STM32F103C6T6 Hardware Design and Validation Checklist

This is a proposed validation procedure, not author-run experimental data. Report the test hardware, operating conditions, raw readings, instruments, and measurement uncertainty.

Minimum Hardware Checklist

• Connect VDD pins 24, 36, and 48 to 3.3 V and VSS pins 23, 35, and 47 to ground. Place one 100 nF capacitor at each VDD/VSS pair and at least 4.7 µF bulk capacitance on the 3.3 V rail.

• Connect VDDA pin 9 to 3.3 V and VSSA pin 8 to ground. Decouple VDDA with 100 nF + 1 µF.

• If VBAT is unused, connect pin 1 to VDD and decouple it with 100 nF.

• Hold BOOT0 pin 44 low with a 10 kΩ pull-down for normal Flash boot.

• Connect NRST pin 7, PA13/SWDIO pin 34, and PA14/SWCLK pin 37 to the SWD interface. Add 100 nF from NRST to ground.

• Use HSI for basic bring-up. Add the appropriate HSE/LSE circuit when required by the final clock configuration.

Minimum-System Schematic

Figure 5. STM32F103C6T6 Minimum-System Schematic

Figure 5 should show all power pins, decoupling capacitors, VDDA/VSSA, VBAT, BOOT0, NRST, and SWD connections.

Test Conditions to Record

Record the board revision, sample count n, repetitions, supply voltage and ripple, ambient temperature, clock configuration, loads, probe setup, instrument accuracy and calibration status, firmware build, STM32Cube versions, compiler version, and ST-LINK firmware version.

Calculation and Validation Checklist

For the 12-bit ADC, where VSSA ≈ 0 V:

LSB=V_DDA/4096

N_ideal= min (4095, [ (4096 x V_IN)/V_DDA ] )

where:

• Nideal = ideal ADC code

• VIN = applied ADC input voltage

• VDDA = measured analog supply/reference voltage

The ADC result must remain within 0 to 4095.

Code error = Nmeasured − Nideal

For an edge-aligned, up-counting timer:

fTIM = PCLKx, when the APB prescaler = 1

fTIM = 2 × PCLKx, when the APB prescaler > 1

Then:

fPWM = fTIM/([(PSC + 1) × (ARR + 1)])

For PWM mode 1, active-high operation:

Duty cycle (%) = CCRx/(ARR + 1) x 100

where PSC is the timer prescaler, ARR is the auto-reload value, and CCRx is the capture/compare value.

For measured ADC, PWM, or timing results:

Error (%) = (Measured - Expected)/Expected x 100

Report the signed or absolute error together with the measurement uncertainty and test conditions.

Third-Party Research Case Studies

These case studies summarize third-party research using the STM32F103C6T6. They were not completed or measured by the author of this article.

Magnetic Capsule Control

Wang et al. (2023) used STM32-generated PWM to control three orthogonal Helmholtz-coil pairs through three H-bridge modules rated at 450 W each and supplied at 30 V. The 450 W value was a module rating, not measured power consumption. The system used open-loop control rather than closed-loop current or orientation feedback.

Tests used a Ø25 × 58 mm capsule in a 100 mm water cube. Two cameras recorded motion at 640 × 480 pixels and 60–900 fps. The capsule demonstrated 90° rotations. At 5 mT, the reported maximum soft-magnet torque estimate was 6 × 10⁻⁵ N·m, compared with 5.4 × 10⁻³ N·m for the permanent magnet. Torque was estimated from rotation behavior rather than measured with a torque sensor. Independent specimen count, trial count, uncertainty, and numerical orientation error were not reported.

Source: Wang, Cui, Tian, and Han (2023).

Haptic Touchscreen Control

Kim et al. (2022) used an STM32F103C6T6 to control an electrostatic resonant actuator. One prototype attached to a 125 g block was measured with a 352C66 accelerometer during a 50–200 Hz sweep, reaching 2.5 g at 99 Hz, where g denotes acceleration.

Four actuators were then tested on one 17-inch panel at 25 locations and 90, 117, and 150 Hz, giving 75 location-frequency conditions rather than 75 independent samples. Reported peaks were 1.4 g, 2.6 g, and 1.5 g, respectively. The paper identifies the oscilloscope as DPO2012B in a figure but DPO2021B in the text. Repetitions, uncertainty, human testing, lifetime, and power consumption were not reported.

Source: Kim et al. (2022).

Common Problems and Documented Troubleshooting Steps

STM32F103C6T6 vs STM32F103C8T6

The main differences between the STM32F103C6T6 and STM32F103C8T6 are memory capacity and the number of available timers and communication peripherals.

The C6T6 and C8T6 share the LQFP48 footprint and STM32F103 architecture, but migration still requires verification of the exact linker script, startup files, alternate functions, peripheral availability, electrical limits, and applicable errata. C8 firmware cannot be moved to C6 unchanged when it exceeds 32 KB of Flash or 10 KB of SRAM, or uses TIM4, I²C2, USART3, or SPI2.

LQFP48 Mechanical Dimensions

Figure 6. LQFP48 7 × 7 mm package outline and mechanical data

The STM32F103C6T6 uses a 48-pin LQFP package with a typical body size of 7 × 7 mm. Its typical overall width, including the leads, is 9 × 9 mm, with a 0.50 mm pin pitch and a maximum package height of 1.60 mm. Each lead is typically 0.60 mm long, with an allowed range of 0.45–0.75 mm.

Note: All dimensions are in millimetres, and the drawing is not to scale. The minimum and maximum values show manufacturing tolerances. Use ST’s recommended PCB footprint instead of calculating the solder pads directly from the package outline. Pin 1 must also match the identification mark on the device.

Technical References

• STMicroelectronics. STM32F103x4, STM32F103x6: Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces. DS5936/DocID15060, Rev. 7, June 2015.

• STMicroelectronics. STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm-based 32-bit MCUs. RM0008, Rev. 21, February 2021.

• STMicroelectronics. STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual. PM0056, Rev. 7, December 2024.

• STMicroelectronics. STM32F10xxx Flash memory microcontrollers. PM0075, Rev. 2, August 2012.

• STMicroelectronics. Getting started with STM32F10xxx hardware development. AN2586, Rev. 8, December 2022.

• STMicroelectronics. STM32F103x8, STM32F103xB: Medium-density performance line. DS5319, Rev. 20, July 2025.