The CD4093B is a widely used CMOS logic IC that combines four independent 2-input NAND gates with built-in Schmitt trigger inputs, making it suitable for stable and reliable digital signal processing. This article will discuss the CD4093B IC, including its features, pinout, specifications, internal diagrams, logic operation, and practical circuit implementation.

The CD4093B is a CMOS integrated circuit that contains four independent 2-input NAND gates, each designed with Schmitt trigger inputs. It operates over a wide voltage range and provides stable switching behavior, even when input signals change slowly or contain noise. Compared to the original CD4093, the CD4093B is an improved version, offering better electrical performance, enhanced stability, and more consistent characteristics across operating conditions.
Each gate in the CD4093B switches at different threshold levels for rising and falling signals, a feature known as hysteresis. This improves signal integrity by reducing unwanted transitions and ensuring clean digital outputs. The device is available in multiple standard packages, making it suitable for various circuit designs while maintaining low power consumption typical of CMOS technology.
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| Pin No. | Pin Name | Description |
| 1 | A | Input A (Gate 1) |
| 2 | B | Input B (Gate 1) |
| 3 | Y1 | Output (Gate 1) |
| 4 | A2 | Input A (Gate 2) |
| 5 | B2 | Input B (Gate 2) |
| 6 | Y2 | Output (Gate 2) |
| 7 | VSS | Ground (0V) |
| 8 | Y3 | Output (Gate 3) |
| 9 | B3 | Input B (Gate 3) |
| 10 | A3 | Input A (Gate 3) |
| 11 | Y4 | Output (Gate 4) |
| 12 | B4 | Input B (Gate 4) |
| 13 | A4 | Input A (Gate 4) |
| 14 | VDD | Supply Voltage |
Each input includes built-in Schmitt trigger action, allowing the IC to handle slow or noisy signals without requiring external components.
The device provides stable switching with typical hysteresis of 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V, improving signal reliability.
It offers noise immunity greater than 50% of the supply voltage, ensuring strong resistance to signal disturbances.
There is no restriction on input rise and fall times, making it suitable for a wide range of signal conditions.
Standardized and balanced output performance ensures consistent behavior in digital circuits.
The IC is 100% tested for quiescent current at 20 V, supporting efficient low-power operation.
Maximum input current is 1 µA at 18 V across the full temperature range, and 100 nA at 25°C, minimizing input loading.
Supports 5 V, 10 V, and 15 V parametric ratings, providing design flexibility.
Fully meets JEDEC Standard No. 13B for “B” series CMOS devices, ensuring quality and reliability.
| Category | Parameter | Value |
| General | Logic Type | Quad 2-input NAND with Schmitt trigger |
| Number of Gates | 4 | |
| Inputs per Gate | 2 | |
| Technology | CMOS | |
| Supply | Operating Voltage (VDD) | 3 V to 18 V |
| Absolute Max VDD | −0.5 V to +20 V | |
| Input | Input Voltage Range | −0.5 V to VDD + 0.5 V |
| Input Current | ≤1 µA at 18 V (≤100 nA at 25°C) | |
| Output | Output Voltage (VOH/VOL) | Close to VDD / VSS |
| Power Dissipation | 100 mW per output transistor | |
| Hysteresis | Hysteresis Voltage (VH) | ~0.9 V (5 V), ~2.3 V (10 V) |
| Switching | Propagation Delay | ~60 ns to 200 ns |
| Rise/Fall Time | No limit (Schmitt trigger input) | |
| Current | DC Input Current (Max) | ±10 mA |
| Quiescent Current (IDD) | Very low (CMOS level) | |
| Thermal | Thermal Resistance (θJA) | ~76°C/W to 86°C/W |
| Temperature | Operating Temp (TA) | −55°C to +125°C |
| Storage Temp (Tstg) | −65°C to +150°C | |
| Lead Temp (Soldering) | +265°C (10 sec max) | |
| Package | Package Types | DIP-14, SOIC-14, TSSOP-14 |
| Compliance | Standard | JEDEC Standard No. 13B |

Functional block diagram of the CD4093B shows four independent NAND gates, each with two inputs and one output. These gates are internally arranged in a symmetrical structure, where each pair of inputs is processed through a Schmitt trigger stage before reaching the NAND logic. This means the input signals are first stabilized, ensuring clean transitions even if the signals are slow or noisy.
Each NAND gate operates separately, allowing multiple logic functions to run at the same time within a single IC. The diagram also highlights the power connections, with VDD supplying the positive voltage and VSS acting as ground. Overall, the internal structure emphasizes reliable switching behavior and consistent logic output due to the built-in hysteresis at each input stage.

The logic diagram of the CD4093B represents one of its Schmitt trigger input stages. It shows how the input signal passes through a network of transistors and resistive elements before reaching the logic gate. The presence of feedback inside this structure creates hysteresis, meaning the switching threshold is different for rising and falling signals. This ensures that the output changes state only when the input crosses well-defined voltage levels.
The diagram also includes protection diodes connected to VDD and VSS, which help protect the input from voltage spikes and ensure safe operation within the allowed range. Overall, this internal design improves noise immunity and allows the IC to produce clean and stable digital outputs even when the input signal is not ideal.
The CD4093B is a quad 2-input NAND gate IC with built-in Schmitt trigger inputs. Each gate operates based on NAND logic, where the output is LOW only when both inputs are HIGH. In all other input conditions, the output remains HIGH. This behavior makes NAND logic the inverse of an AND gate, providing a complement output.
Internally, the CD4093B contains four independent NAND gates connected to specific input and output pins. For example, pins 1 and 2 act as inputs for one gate, while pin 3 provides the corresponding output. The same structure is repeated across the IC, allowing multiple logic operations within a single device. In addition to standard NAND operation, the Schmitt trigger input ensures stable switching by introducing hysteresis, which improves signal reliability when inputs are slow or noisy.
The truth table below represents the logic behavior of each NAND gate inside the CD4093B:
| Input A | Input B | Output |
| 0 | 0 | 1 |
| 1 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 0 |
This table confirms that the output only goes LOW when both inputs are HIGH, which defines the fundamental operation of the CD4093B.

In this circuit, the CD4093B is used as a timing and control element to create a delay before activating the relay. The first NAND gate (U1A) works together with the RC network (R1, R2, and C1). When power is applied, capacitor C1 starts charging through R1, and because the CD4093B has Schmitt trigger inputs, it waits until the voltage reaches a defined threshold before switching its output. This creates a stable and predictable delay.
The delay time is approximately defined by the formula:
T ≈ 0.7 × R1 × C1
Which is why R1 is labeled as “time adjust.”
Once the threshold is reached, the output of U1A changes state and feeds the second NAND gate (U2A), which acts as a buffer/inverter. This output then drives transistor Q1, turning it ON.
When Q1 turns ON, it energizes the relay coil, switching the load. Diodes (D3, D4, D5) protect the circuit from voltage spikes, while the LED indicates power status. Overall, the CD4093B ensures clean switching and accurate timing using its Schmitt trigger behavior.