075582814553
The CD40106B is a CMOS hex Schmitt-trigger inverter designed to provide reliable digital signal inversion with improved noise immunity. As part of the 4000B CMOS logic family, this device integrates six independent inverter gates in a single IC, each featuring a Schmitt-trigger input that introduces hysteresis. This article will discuss CD40106B overview, variants, functional operation, specifications, key working principles, and more.
The CD40106B CMOS Hex Schmitt-Trigger Inverters is a digital logic integrated circuit that contains six independent inverter gates, each designed with a Schmitt-trigger input. This structure allows the device to switch at different voltage thresholds for rising and falling signals, creating a hysteresis effect that improves signal stability. Each gate outputs the opposite logic level of its input while maintaining reliable switching behavior even with slow or noisy input signals.
The CD40106B is an improved version of the CD40106, offering enhanced electrical performance and better CMOS B-series characteristics. It provides improved switching reliability, more stable threshold levels, and wider operating conditions compared with the earlier device. The IC is typically available in several package types and supports a broad operating temperature range, making it suitable for various digital circuit designs that require dependable logic inversion with built-in hysteresis.
If you are interested in purchasing the CD40106B, feel free to contact us for pricing and availability.
| Part Number | Package Type | Pin Count | Body Size (Nominal) |
| CD40106B | CDIP | 14 Pins | 6.92 mm × 19.94 mm |
| CD40106BE | PDIP | 14 Pins | 6.30 mm × 19.31 mm |
| CD40106BM | SOIC | 14 Pins | 3.90 mm × 8.65 mm |
| CD40106BNSR | SO | 14 Pins | 5.30 mm × 10.20 mm |
| CD40106BPWR | TSSOP | 14 Pins | 4.40 mm × 5.00 mm |
| Pin Number | Pin Name | Description |
| 1 | A | Input of inverter gate 1 |
| 2 | G (Ā) | Output of inverter gate 1 |
| 3 | B | Input of inverter gate 2 |
| 4 | H (B̅) | Output of inverter gate 2 |
| 5 | C | Input of inverter gate 3 |
| 6 | I (C̅) | Output of inverter gate 3 |
| 7 | VSS | Ground (0 V reference) |
| 8 | J (D̅) | Output of inverter gate 4 |
| 9 | D | Input of inverter gate 4 |
| 10 | K (E̅) | Output of inverter gate 5 |
| 11 | E | Input of inverter gate 5 |
| 12 | L (F̅) | Output of inverter gate 6 |
| 13 | F | Input of inverter gate 6 |
| 14 | VDD | Positive supply voltage |
| Equivalent / Alternative IC | Manufacturer/Family | Notes |
| HEF40106B | Nexperia | CMOS hex Schmitt-trigger inverter equivalent to CD40106B |
| HCF40106B | STMicroelectronics | Functionally compatible CMOS Schmitt-trigger inverter |
| MC140106B / MC14106B | ON Semiconductor / Motorola | Equivalent 4000-series logic IC |
| TC40106BP | Toshiba | Same logic function and pin configuration |
| NTE40106B | NTE Electronics | Replacement part with the same functionality |
| 74C14 | 74C CMOS family | Similar hex Schmitt-trigger inverter, but with slightly different electrical characteristics |
| 74HC14 | High-speed CMOS 74 series | Same logic function but typically operates at lower supply voltages |
| MC14584B / CD4584B | CMOS Schmitt trigger inverter family | Similar logic function depending on design requirements |
The functional block diagram of the CD40106B shows six independent inverter circuits, each designed with a Schmitt-trigger input stage. Every inverter has a single input (A, B, C, D, E, or F) and a corresponding output (G, H, I, J, K, or L). The inputs pass through a Schmitt-trigger symbol before reaching the inverter stage, indicating that the circuit includes hysteresis to stabilize switching behavior. The device operates with VDD connected to Pin 14 as the supply voltage and VSS connected to Pin 7 as ground.
In this configuration, each inverter performs the Boolean logic function Y = Ā, meaning the output is the logical opposite of the input signal. When the input voltage rises above the upper threshold, the output switches to a low level. When the input voltage falls below the lower threshold, the output switches to a high level. This separation between switching thresholds helps prevent false triggering caused by noise or slow signal transitions.
The truth table confirms this behavior. When the input is High (H), the output becomes Low (L). Conversely, when the input is Low (L), the output becomes High (H). This simple inversion function, combined with the Schmitt-trigger input, allows the CD40106B to provide stable and reliable digital signal inversion.
| Category | Parameter | Specification |
| General Information | Product Model | CD40106B |
| Logic Family | CMOS 4000B Series | |
| Logic Type | Hex Schmitt-Trigger Inverter | |
| Number of Functions | 6 Inverters | |
| Number of Channels | 6 | |
| Lifecycle Status | Active | |
| Electrical Characteristics | Supply Voltage (VDD) | 3 V – 18 V |
| Absolute Maximum Supply Voltage | −0.5 V to 20 V | |
| Logic Level High | 3.6 V – 10.8 V | |
| Logic Level Low | 0.9 V – 4 V | |
| Output Current (Max) | 6.8 mA | |
| Input Capacitance | 5 pF | |
| Load Capacitance | 50 pF | |
| Quiescent Current | 40 nA | |
| Max Supply Current (ICC) | 0.12 mA | |
| Timing Characteristics | Propagation Delay | 120 ns |
| Turn-On Delay Time | 280 ns | |
| Thermal Characteristics | Maximum Junction Temperature | 150 °C |
| Operating Temperature Range | −55 °C to 125 °C | |
| Storage Temperature | −65 °C to 150 °C | |
| Power Dissipation | 100 mW | |
| ESD Protection | Human Body Model (HBM) | 2000 V |
| Charged Device Model (CDM) | 1000 V | |
| Package & Mechanical | Package Type | DIP-14 |
| Mounting Type | Through Hole | |
| Pin Count | 14 Pins | |
| Terminal Pitch | 2.54 mm | |
| Length | 19.3 mm | |
| Width | 6.35 mm | |
| Height | 5.08 mm | |
| Compliance & Standards | RoHS Status | RoHS3 Compliant |
| Moisture Sensitivity Level | MSL 1 (Unlimited) | |
| ECCN Code | EAR99 | |
| Lead Finish | Gold / Lead-Free |
The CD40106B features built-in Schmitt-trigger inputs on each inverter gate. This design provides two different switching thresholds for rising and falling signals, which improves signal stability and prevents unwanted switching caused by noise or slow input transitions.
The device provides a clear hysteresis voltage that varies depending on the supply voltage. Typical hysteresis values are about 0.9 V at 5 V, 2.3 V at 10 V, and 3.5 V at 15 V. This characteristic allows the IC to filter unstable signals and maintain reliable switching behavior.
The CD40106B offers noise immunity greater than 50% of the supply voltage, allowing the device to operate reliably even when signals contain electrical noise or interference.
The IC does not require strict input rise or fall time limits. This means it can handle slowly changing input signals without causing oscillation or unstable switching.
The device provides standardized and symmetrical output characteristics, allowing balanced switching performance for both high and low output states.
The CD40106B operates with very low quiescent current even at higher supply voltages. This helps reduce overall power consumption in electronic circuits.
The maximum input current is approximately 1 µA at 18 V over the full temperature range, and about 100 nA at 18 V and 25°C, ensuring minimal loading on input signals.
The IC supports 5 V, 10 V, and 15 V parametric ratings, allowing it to operate across a wide range of supply voltages for flexible digital circuit design.
To utilize the CD40106B, the device must first be powered correctly by connecting the supply voltage (VDD) to Pin 14 and the ground (VSS) to Pin 7. The IC operates within a wide supply voltage range, typically from 3 V to 18 V, allowing it to work in many digital circuit environments. Providing a stable power source ensures proper switching performance and reliable operation of the internal CMOS circuitry.
After powering the device, an input signal can be applied to any of the inverter input pins labeled A, B, C, D, E, or F. Each input passes through a Schmitt-trigger stage before reaching the inverter, which helps stabilize the signal by introducing hysteresis. This design allows the CD40106B to handle slow-changing or noisy signals without producing unwanted switching behavior.
The corresponding output pins G, H, I, J, K, and L produce the inverted logic level of the input signals. When the input is high, the output becomes low, and when the input is low, the output becomes high. Because the device includes six independent inverter gates, multiple signals can be processed within a single IC, making the CD40106B a compact and efficient solution for digital signal inversion and conditioning.
How one inverter inside the CD40106B can be used to drive a simple charge-pump voltage circuit? Inside the dashed block, the CD40106B inverter consists of two CMOS transistors (Q1 and Q2) that switch alternately when an input signal VIN is applied. When the input changes state, the inverter produces a switching output at VOUT1, creating a square-wave signal between ground and the supply voltage.
This switching signal is then used to control the external diode-capacitor network formed by D1, D2, C1, and COUT. When the inverter output goes high or low, capacitor C1 charges and transfers energy through the diodes. The diodes ensure current flows in only one direction, allowing the circuit to store charge and build a higher voltage level at the output capacitor COUT.
As the switching continues, the capacitor network accumulates charge and produces a stabilized output voltage VOUT. In this application, the CD40106B acts as a switching driver, while the external components convert the switching signal into a boosted or conditioned DC voltage.
• Signal conditioning
• Waveform shaping
• Oscillation generation
• Switch debouncing
• Pulse generation
• Timing control
• Noise suppression
• Frequency generation
• Digital logic inversion
• Clock generation
• Voltage multiplication
• Signal stabilization
| Parameter | CD40106B | 74HC14 |
| Logic Family | CMOS 4000B Series | High-Speed CMOS (74HC Series) |
| Function | Hex Schmitt-Trigger Inverter | Hex Schmitt-Trigger Inverter |
| Number of Inverters | 6 | 6 |
| Supply Voltage Range | 3 V – 18 V | 2 V – 6 V |
| Typical Operating Voltage | 5 V, 10 V, 15 V | 5 V |
| Propagation Delay | ~120 ns | ~15 ns |
| Switching Speed | Lower | Much Faster |
| Input Type | Schmitt Trigger | Schmitt Trigger |
| Noise Immunity | High | High |
| Output Current | ~6.8 mA | ~20 mA |
| Power Consumption | Very Low (CMOS) | Low |
| Package Options | DIP, SOIC, TSSOP | DIP, SOIC, TSSOP |
| Main Advantage | Wide voltage operation | High-speed switching |
The CD40106B CMOS Hex Schmitt-Trigger Inverter provides a reliable and efficient solution for digital logic inversion while maintaining excellent noise immunity and stable switching performance. Its Schmitt-trigger inputs, low power consumption, and wide operating voltage range make it a versatile component for many digital electronics designs. By integrating six independent inverter gates in one package, the device allows multiple signals to be processed efficiently within compact circuit layouts.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other