01
Basically, it's good to separate modules and numbers. Care should be taken not to cross the MOAT and not to let the power supply and signal return current path grow too large.
Crystal oscillator is a simulated positive feedback oscillation circuit. To have a stable oscillation signal, loop gain and phase specifications must be met. However, the oscillating specifications of the analog signals are very susceptible to interference, which may not be completely isolated even with ground guard traces. And too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. Therefore, be sure to put the crystal oscillator and chip distance into possible close.
It is true that there are many conflicts between high-speed wiring and EMI requirements. However, the basic principle is that due to the resistance capacitance or Ferrite Bead added by EMI, some electrical characteristics of the signal cannot be caused to fail to meet the specifications. Therefore, it is best to use the technique of arranging wiring and PCB stacking to solve or reduce EMI problems, such as high-speed signal lining. Finally, resistor capacitance or Ferrite Bead method was used to reduce the damage to the signal.
02
Nowadays, most of the automatic cabling devices in strong cabling software have set constraints to control the winding mode and the number of holes. EDA companies sometimes vary widely in setting the capabilities and constraints of winding engines. For example, whether there are enough constraints to control how serpentine lines wind, whether there are enough constraints to control the spacing of difference pairs, etc. This will affect whether the automatic wiring out of the wiring can conform to the designer's idea.
In addition, the difficulty of manual wiring adjustment is also absolutely related to the ability of the winding engine. For example, the wire pushing capacity, through the hole pushing capacity, and even the wire on copper coating pushing capacity and so on. So, choose a cabler with strong winding engine ability, it is the way to solve.
03
Generally in the blank area copper coating most of the case is grounded. Just pay attention to the distance between copper and the signal line when copper is applied next to the high-speed signal line, because the copper applied will reduce the characteristic impedance of the line. Also be careful not to affect the characteristic impedance of other layers, as in the dual strip line construction.
04
Yes, both the power plane and the ground plane must be considered as reference planes when calculating the characteristic impedance. For example, four-layer board: top layer - power layer - stratum - bottom layer. In this case, the model of top layer's wiring characteristic impedance is a microstrip line model with power plane as reference plane.
05
Whether the test points generated automatically by general software can meet the test needs depends on whether the specifications of the added test points meet the requirements of the testing machine. In addition, if the wiring is too dense and the specification for adding test points is strict, it may not be possible to automatically add test points to each segment of the line. Of course, you need to manually complete the test areas.
06
Whether it affects the signal quality depends on how the test points are added and how fast the signal is. Basically, the added test point does not use the existing perforation (via or DIP pin) as the test point. It may be added to or pulled from the line. The former is equivalent to adding a very small capacitor in line, the latter is an extra branch.
Both of these two conditions have more or less influence on high-speed signals, and the degree of influence is related to the frequency speed and edge rate of signal. The influence can be obtained through simulation. In principle, the smaller the test point, the better (of course, to meet the requirements of the test machine) the shorter the branch, the better.
07
When the signal or power supply between each PCB board is connected to each other, for example, A board has power supply or signal to B board, there must be an equal amount of current from the floor flow back to A board (this is Kirchoffcurrent law). The current in this layer will find its way back to the lowest impedance. Therefore, the number of pins assigned to the formation should not be too low at each interface, either power or signal connection, to reduce impedance and thus reduce formation noise.
It is also possible to analyze the entire current loop, especially the larger part of the current, and adjust the connection of the ground or ground to control the flow of the current (for example, to create a low impedance in one place so that most of the current flows through that place), reducing the impact on other more sensitive signals.
08
chassis ground to provide a path of low impedance to return current anThe principle of selecting PCB and shell ground is to use d control the return current. For example, usually in the vicinity of high frequency devices or clock generators, fixed screws can be used to connect the PCB ground to the chassis ground, so as to minimize the entire current loop area and reduce electromagnetic radiation.
09
As far as digital circuits are concerned, three things must first be determined in order:
(1)Make sure that all power supply values meet the design requirements. Some systems with multiple power supplies may require a certain order and speed between the power supplies;
(2)Ensure that all clock signal frequencies are working properly and there are no non-monotonic problems on signal edges;
(3)Verify that the reset signal meets the specification requirements.
If all this is normal, the chip should signal the first cycle. Then DEBUG according to the operating principle of the system and bus protocol.
10
In the case of the fixed size of the circuit board, if the design needs to accommodate more functions, it is often necessary to improve the PCB routing density, but this may lead to increased mutual interference of routing, at the same time, too thin wiring can not reduce the impedance.
Crosstalkinterference is important in designing high-speed and high-density PCBS because it has a great impact on timing and signal integrity. Here are a few things to look out for:
Control the continuity and matching of wiring characteristic impedance. Distance between cables. The spacing commonly seen is twice the line width. The effect of the spacing on timing and signal integrity can be known through simulation, and the minimum allowable spacing can be found. Signals from different chips may have different results.
Select an appropriate termination mode. Do not allow the two adjacent layers to have the same direction, or even overlap with each other, because crosstalk is larger than that of adjacent layers.
Blind /buried via is used to increase the wiring area. But the cost of PCB board production will increase. It's really hard to do exactly parallel and equal length in practice, but try to do it anyway.