075582814553
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
| Series | MAX 7000 | Maximum Operating Temperature | + 70 C |
|---|---|---|---|
| Memory Type | EEPROM | Minimum Operating Temperature | 0 C |
| Number of Macrocells | 64 | Package / Case | TQFP-100 |
| Maximum Operating Frequency | 222.2 MHz | Mounting Style | SMD/SMT |
| Delay Time | 4.5 ns | Packaging | Tray |
| Number of Programmable I/Os | 68 | Supply Voltage Max | 3.6 V |
| Operating Supply Voltage | 3.3 V | Supply Voltage Min | 3 V |
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 