The 74AUP1G08GW is a low-power 2-input AND Gate, Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Feature
High noise immunity
Complies with JEDEC standards - JESD8-12, JESD8-11, JESD8-7, JESD8-5, JESD8-B
ESD Protection - HBM JESD22-A114F >5000V, MM JESD22-A115-A >200V, CDM JESD22-C101E >1000V
0.9µA Low static power consumption (ICC)
Latch-up performance exceeds 100mA per JESD 78 Class II
Inputs accept voltages up to 3.6V
<10% of VCC Low noise overshoot and undershoot
IOFF circuitry provides partial power-down mode operation
Applications
Industrial
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
