The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPSanalog-to-digital converter (ADC) with an on-chip sampleand-holdcircuit designed for low cost, low power, small size,and ease of use. The product operates at a conversion rate ofup to 125 MSPS and is optimized for outstanding dynamicperformance and low power in applications where a smallpackage size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.

The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) forcapturing data on the output and a frame clock output (FCO)for signaling a new output byte are provided. Individual-channelpower-down is supported and typically consumes less than 2 mWwhen all channels are disabled. The ADC contains several featuresdesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digitaltest pattern generation. The available digital test patternsinclude built-in deterministic and pseudorandom patterns, alongwith custom user-defined test patterns entered via the serial portinterface (SPI).

The AD9253 is available in a RoHS-compliant, 48-lead LFCSP.It is specified over the industrial temperature range of −40°C to+85°C. This product is protected by a U.S. patent.

Product Highlights

• Small Footprint. Four ADCs are contained in a small, spacesaving package.

• Low power of 110 mW/channel at 125 MSPS with scalable power options.

• Pin compatible to the AD9633 12-bit quad ADC.

• Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation.

• User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements

Feature

• 1.8 V supply operation

• Low power: 110 mW per channel at 125 MSPS with scalable power options

• SNR = 74 dB (to Nyquist)

• SFDR = 90 dBc (to Nyquist)

• DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)

• Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)

• 650 MHz full power analog bandwidth

• 2 V p-p input voltage range

• Serial port control

• Full chip and individual channel power-down modes

• Flexible bit orientation

• Built-in and custom digital test pattern generation

• Multichip sync and clock divider

• Programmable output clock and data alignment

• Programmable output resolution

• Standby mode

AD9253-EP supports defense and aerospace applications (AQEC standard)

• Download(pdf)

• Military temperature range (−55°C to +125°C)

• Controlled manufacturing baseline

• Qualification data available on request

• V62/13627 DSCC Drawing Number

Applications

• Medical imaging and nondestructive ultrasound

• Quadrature radio receivers

• Diversity radio receivers

• Optical networking

• Test equipment