This device includes two specialized MOSFETs in a unique dual Power 56 package. It is designed to provide an optimal synchronous buck power stage in terms of efficiency and PCB utilization. The low switching loss “High Side” MOSFET is complementory by a low conduction loss “Low Side” SyncFET.
Feature
Q1: N-Channel Max rDS(on) = 20.0 mΩ at VGS = 10 V, ID = 10.1 AMax rDS(on) = 30.0 mΩ at VGS = 4.5 V, ID = 7.5 A
Q2: N-Channel Max rDS(on) = 11.2 mΩ at VGS = 10 V, ID = 12.4 AMax rDS(on) = 14.2 mΩ at VGS = 4.5 V, ID = 10.9 A
Pinout optimized for simple PCB design
Thermally efficient dual Power 56 Package
RoHS Compliant
Applications
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
