The 74HC160D is a CMOS 4-bit synchronous decade counter that can count from 0 to 9 with a synchronous count input and an asynchronous reset input. This high-speed Si-gate CMOS device aligns with low-power Schottky TTL (LSTTL) pins. It meets the requirements of JEDEC standard no. 7A. These counters' outputs (Q0 through Q3) can be set to either a HIGH or LOW state. When the parallel enable input (PE) is at a LOW state, it halts the count and lets input data (D0 through D3) load into the counter as the clock edge rises, as long as the setup and hold time criteria for PE are satisfied. This presetting occurs irrespective of the states at the count enable inputs (CEP and CET). For more details about this presettable counter pinout, circuit diagram, etc can check the 74HC160D datasheet. It's widely used for counting and timing applications.

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