The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824

bits.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration
of an Activate command, which is followed by a Read or Write command. The address bits registered
coincident with the activate command are used to select the bank and row to be accesses (BA0-BA2 select
the bank, A0-A13 select the row). The address bits registered coincident with the Read or Write command
are used to select the starting column location for the burst access and to determine if the Auto-Precharge

command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command description and device operation.