The DS21348T+ from Maxim Integrated Products is a 3.3V E1/T1/J1 line interface in 44 pin TQFP package. It is a complete selectable E1 or T1 line interface unit for short-haul and long-haul applications. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1 waveshapes in 75ohm or 120 ohm applications and DSX-1 line build-outs or CSU line build-outs of 0dB, -7.5dB, -15dB, -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications. The jitter attenuator FIFO is selectable to either 32bits or 128bits in depth and can be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK is available for use as a backplane system clock.
Feature
3.3V power supply, 50mA (RMS) current limiter, operating temperature range from 0°C to 70°C
32bit/128bit crystal less jitter attenuator requires 2.048MHz master clock for both E1 and T1
Generates line build-outs with and without return loss for E1, DSX-1, CSU line build-outs for T1
AMI, HDB3 and B8ZS, encoding/decoding
16.384MHz, 8.192MHz, 4.096MHz or 2.048MHz clock output synthesized to recovered clock
Programmable monitor mode for receiver, NRZ/bipolar interface for Tx/Rx data I/O
Loopbacks and PRBS pattern generation/ detection with output for received errors
Generates/detects In-band loop codes, 1 to 16bit including CSU loop codes, RCL indication
8bit parallel or serial interface with optional hardware mode, transmit open-circuit detection
Muxed and nonmuxed parallel bus supports Intel or Motorola, detects/generates blue (AIS) alarms
Signal Processing
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
