The µPD4702 is 8-bit up/down counters for an incremental encoder. Two-phase (A, B) incremental input signals are phase-differentiated, and on each signal edge, an up-count is executed if the A phase is leading, or a down-count if the B phase is leading. Eight-bit count data is output in real time. A carry output and borrow output are also provided for counter overflow and underflow.
The µPD4704 is also available; use of these enables the count width to be extended.
Feature
• Incremental inputs (A, B)
• On-chip phase discrimination circuit (up-count mode
when the phase order is A → B, down-count mode
when B → A) 4-multiplication count method
• On-chip edge detection circuit
• 8-bit up/down counter latch output o Carry output, borrow output
• Count data output controllable (3-state output)
• CMOS, single +5 V power supply
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
