Feature
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ 990 mW (max)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2
■ Available in Pb-free and non Pb-free 54-pin TSOP II package
and non Pb-free 60-ball fine-pitch ball grid array (FBGA) package
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
