As a new-generation industry-specific SoC designed for the HD IP camera, Hi3519 V101 integrates a newgeneration ISP and uses the latest H.265 video compression encoder in the industry as well as advanced lowpower technology and architecture design. These features enable Hi3519 V101 to continuously maintain the leading position in the aspects of low bit rate, high picture quality, and low power consumption. Hi3519 V101 supports 90° or 270° rotation and lens distortion correction by using hardware, which meet requirements in various surveillance application scenarios. It also supports 3A algorithms, which allow customers to design various models of IP cameras that contain integrated camera cores. Hi3519 V101 integrates the POR, RTC, and audio CODEC and supports various sensor levels and clock outputs, which significantly reduces the EBOM cost of the HD IP camera based on Hi3519 V101. The Hi3519 V101 HiSilicon SDK features high stability and ease of use, supports rapid mass production, and facilitates system layout of DVRs, NVRs, and IP cameras.
Feature
Processor Core
800 MHz A7 core, supporting 32 KB I-cache, 32 KB Dcache, and 128 KB L2 cache
1.25G GHz A17 core, supporting 32 KB I-cache, 32 KB
D-cache, and 256 KB L2 cache
Neon acceleration, integrated FPU
ARM@big-LITTLE architecture
Video Encoding
H.264 BP/MP/HP
H.265 Main Profile
I/P/B frame, dual-P-frame reference
MJPEG/JPEG baseline encoding
Video Encoding Performance
Maximum 16-megapixel (4608 x 3456) resolution for
H.264/H.265 encoding
Real-time multi-stream H.264/H.265 encoding capability:
3840 x 2160@30 fps+1080p@30 fps + 3840 x 2160@2fps snapshot
Maximum JPEG snapshot performance of 3840 x 2160@30 fps
CBR, VBR, FIXQP, AVBR, and QPMAP modes
Maximum100 Mbit/s output bit rate
Encoding of eight ROIs
Intelligent Video Analysis
Integrated IVE, supporting various intelligent analysis
applications such as motion detection, perimeter defense,
and video diagnosis
Video and Graphics Processing
3D denoising, image enhancement, and dynamic contrast improvement
Anti-flicker for output videos and graphics
1/30x to 16x video scaling
Seamless splicing of 2-channel videos
1/2x to 2x graphics scaling
OSD overlaying of eight regions before encoding
Video graphics overlaying of two layers (video layer and
graphics layer)
ISP
2-channel independent ISP processing
Adjustable 3A functions (AE, AWB, and AF)
FPN removal
Highlight compensation, backlight compensation, gamma correction, and color enhancement
Defect pixel correction, denoising, and digital image stabilization
Anti-fog
Lens distortion correction and fisheye correction
Picture rotation by 90° or 270°
Picture mirroring and flipping
Sensor built-in WDR, 4F/3F/2F frame-based/line-based WDR, and local tone mapping. The second channel of ISP processing supports only sensor built-in WDR, 2F framebased/line-based WDR, and local tone mapping.
ISP tuning tools for the PC
Audio Encoding/Decoding
Voice encoding/decoding complying with multiple protocols by using software
Compliance with the G.711, G.726 and ADPCM protocols
Audio 3A functions (AEC, ANR, and ALC)
Security Engine
AES, DES, and 3DES encryption and decryption
algorithms implemented by using hardware
RSA1024/2048/4096 signature verification algorithm implemented by using hardware
Hash-SHA1/256 and HMAC_SHA1/256 tamper proofing algorithms implemented by using hardware
Integrated 512-bit OTP storage space and hardware random number generator
Video Interfaces
VI Interfaces
− Two sensor inputs. The maximum resolution for the main channel is 16 megapixels (4608 x 3456), and the maximum resolution for the second input is 8 megapixels (4096 x 2160).
− 8-/10-/12-/14-bit RGB Bayer DC timing VI, at most 150 MHz clock frequency
− BT.601, BT.656, or BT.1120 VI interface
− Maximum 12-lane MIPI/LVDS/sub-LVDS/HiSPi interface for the main channel
− Maximum 4-lane MIPI/LVDS/sub-LVDS/HiSPi
interface for the second sensor interface
− Compatibility with mainstream HD CMOS sensors provided by Sony, Aptina, OmniVision, and Panasonic
− Compatibility with the electrical specifications of parallel and differential interfaces of various sensors
− Programmable sensor clock output VO interfaces
− One PAL/NTSC output for automatic load detection
− One BT.1120/BT.656 VO interface for connecting to an external HDMI or SDI, supporting at most 1080p@60 fps output
− LCD output
Audio Interfaces
Integrated audio CODEC supporting 16-bit audio inputs
and outputs
S interface for connecting to an external audio CODEC
Dual-channel differential MIC inputs for reducing
background noises
Peripheral Interfaces
POR
External reset input
Internal RTC
Integrated 3-channel LSADC
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
