• 1 GSPS internal clock speed

• Up to 2 GHz input clock (selectable divide-by-2)

• Integrated 10-bit DAC

• Excellent phase noise and SFDR

• 32-bit programmable frequency register

• Simplified 8-bit parallel and SPI serial control interface

• Automatic frequency sweeping capability

• 4 frequency profiles

• 3.3 V power supply

• Power dissipation: 2 W typical

• Integrated programmable charge pump and phase frequency detector with fast lock circuit

• See data sheet for additional features

• VHF/UHF LO synthesis

• Tuners

• Instrumentation

• Agile clock synthesis

• Cellular base station hopping synthesizers

• Radars

• SONET/SDH clock synthesis

Data Sheet, Rev. C, 2/08