The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD9517-3BCPZ emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9517-3BCPZ features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9517-3BCPZ is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9517-3BCPZ is specified for operation over the industrial range of −40°C to +85°C.
Feature
Low phase noise, phase-locked loop (PLL)On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
2 pairs of 1.6 GHz LVPECL outputsEach output pair shares a 1-to-32 divider with coarse phase delayAdditive output jitter: 225 fs rmsChannel-to-channel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputsEach output pair shares two cascaded 1-to-32 dividers with coarse phase delayAdditive output jitter: 275 fs rmsFine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz CMOS outputs
Automatic synchronization of all outputs on power-up
See datasheet for additonal features
Applications
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
