The AD9958BCPZ-REEL7 consists of two DDS cores that provide independentfrequency, phase, and amplitude control on each channel.This flexibility can be used to correct imbalances betweensignals due to analog processing, such as filtering, amplification,or PCB layout related mismatches. Because both channels sharea common system clock, they are inherently synchronized.Synchronization of multiple devices is supported.

The AD9958BCPZ-REEL7 can perform up to a 16-level modulation offrequency, phase, or amplitude (FSK, PSK, ASK). Modulation isperformed by applying data to the profile pins. In addition, theAD9958BCPZ-REEL7 also supports linear sweep of frequency, phase, oramplitude for applications such as radar and instrumentation.

The AD9958BCPZ-REEL7 serial I/O port offers multiple configurations toprovide significant flexibility. The serial I/O port offers an SPIcompatiblemode of operation that is virtually identical to theSPI operation found in earlier Analog Devices, Inc., DDSproducts. Flexibility is provided by four data pins (SDIO_0 /SDIO_1 / SDIO_2 / SDIO_3) that allow four programmablemodes of serial I/O operation.

The AD9958BCPZ-REEL7 uses advanced DDS technology that provides lowpower dissipation with high performance. The device incorporatestwo integrated, high speed 10-bit DACs with excellent widebandand narrow-band SFDR. Each channel has a dedicated 32-bitfrequency tuning word, 14 bits of phase offset, and a 10-bitoutput scale multiplier.

The DAC outputs are supply referenced and must be terminatedinto AVDD by a resistor or an AVDD center-tappedtransformer. Each DAC has its own programmable reference toenable different full-scale currents for each channel.

The DDS acts as a high resolution frequency divider with theREFCLK as the input and the DAC providing the output. TheREFCLK input source is common to both channels and can bedriven directly or used in combination with an integratedREFCLK multiplier (PLL) up to a maximum of 500 MSPS. ThePLL multiplication factor is programmable from 4 to 20, ininteger steps. The REFCLK input also features an oscillatorcircuit to support an external crystal as the REFCLK source.The crystal must be between 20 MHz and 30 MHz. The crystalcan be used in combination with the REFCLK multiplier.

The AD9958BCPZ-REEL7 comes in a space-saving 56-lead LFCSP package.The DDS core (AVDD and DVDD pins) is powered by a 1.8 Vsupply. The digital I/O interface (SPI) operates at 3.3 V andrequires the pin labeled DVDD_I/O (Pin 49) be connectedto 3.3 V.

The AD9958BCPZ-REEL7 operates over the industrial temperature range of−40°C to +85°C.

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