This section briefly describes the features of the Virtex-5QV family of FPGAs.

Input/Output Blocks (SelectIO Resources)

IOBs are programmable and can be categorized as follows:

• Programmable single-ended or differential (LVDS) operation

• Input block with an optional single data rate (SDR) or double data rate (DDR) register

• Output block with an optional SDR or DDR register

• Bidirectional block

• Per-bit deskew circuitry

• Dedicated I/O and regional clocking resources

• Built-in data serializer/deserializer

The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.

IOBs support the following single-ended standards:

• LVTTL

• LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, and 1.2V)

• PCI (33 and 66 MHz)

• PCI-X

• GTL and GTLP

• HSTL 1.5V and 1.8V (Class I, II, III, and IV)

• HSTL 1.2V (Class 1)

• SSTL 1.8V and 2.5V (Class I and II)

The Digitally Controlled Impedance (DCI) I/O feature can be configured to provide on-chip termination for each single-ended

I/O standard and some differential I/O standards.

The IOB elements also support these differential signaling I/O standards:

• LVDS and Extended LVDS (2.5V only)

• BLVDS (Bus LVDS)

• ULVDS

• HyperTransport™ technology

• Differential HSTL 1.5V and 1.8V (Class I and II)

• Differential SSTL 1.8V and 2.5V (Class I and II)

• RSDS (2.5V point-to-point)