Features Multiple Speed Power,Temperature Options
-Vcc=5 Volts ±10%
-Speeds ranging from 7ns to 25 ns
-Power as low as 37mA at 25MHz
-Commercial and industrial versions available

 CMOS Electrically Erasable Technology
-Superior factory testing
-Reprogrammable in plastic package
-Reduces retrofit and development costs

Development/Programmer Support
-Third party software and programmers
-WinPLACE Development Software
-PLD-to-PEELTM JEDEC file translator

Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
- 20 Pin DIP/SOIC/TSSOP and PLCC

Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary PLDs

General Description

 The PEELTM18CV8 is a Programmable Electrically Erasable Logic (PEELTM) device providing an attractive alternative to ordinary PLDs. The PEELTM18CV8 offers the performance, flex-ibility, ease of design and production practicality needed by logic designers today.
The PEELTM18CV8 is available in 20-pin DIP, PLCC, SOIC andTSSOP packages with speeds ranging from 7ns to 25ns with power consumption as low as 37mA. EE-Reprogrammability provides the convenience of instant reprogramming for develop-
ment and reusable production inventory minimizing the impact of programming changes or errors. EE-Reprogrammability also improves factory testability, thus assuring the highest quality pos-sible.

The PEEL™18CV8 architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides additional architecture features so more logic can be put into every design. Anachip’s JEDEC file translator instantly converts to the PEEL™18CV8 existing 20-pin PLDs without the need to rework the existing design. Development and programming support for the PEEL™18CV8 is provided by popular third-party program- mers and development software.