GENERAL DESCRIPTION 

The ADSP-TS201S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

• An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts

• Four 128-bit internal data buses, each connecting to the six 4M bit memory banks

• On-chip DRAM (24M bit)

• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM

• A 14-channel DMA controller

• Four full-duplex LVDS link ports

• Two 64-bit interval timers and timer expired pin

• An 1149.1 IEEE-compliant JTAG test access port for onchip emulation