These 32-bit automotive microcontrollers are a family of System-on-Chip (SoC) devices that contain many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of this automotive controller family is built on Power Architecture? technology. This family contains enhancements that improve the architecture’s fit in embedded applications, includes additional instruction support for Digital Signal Processing (DSP), integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain applications. The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an External Bus Interface (EBI) for ‘calibration’.
Feature
32-channel Direct Memory Access controller (DMA)
Interrupt Controller (INTC) capable of handling 364 selectable-priority interrupt sources: 191 peripheral interrupt sources, 8 software interrupts and 165 reserved interrupts.
Frequency-Modulated Phase-Locked Loop (FMPLL)
Calibration External Bus Interface (EBI)1
System Integration Unit (SIU)
Up to 1.5 Mbyte on-chip Flash with Flash controller
Up to 94 Kbyte on-chip static RAM (including up to 32 Kbyte standby RAM)
Boot Assist Module (BAM)
32-channel second-generation enhanced Time Processor Unit (eTPU)
16-channels enhanced Modular Input-Output System (eMIOS)
(Picture: Diagram)
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
