3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS

3.0V to 3.6V, -40ºC to +150ºC, DC to 60 MIPS

Modified Harvard Architecture

C Compiler Optimized Instruction Set

16-bit Wide Data Path

24-bit Wide Instructions

16x16 Integer Multiply Operations

32/16 and 16/16 Integer Divide Operations

Two 40-bit Accumulators with Rounding and Saturation Options

Single-Cycle Multiply and Accumulate

Single-Cycle shifts for up to 40-bit Data

16x16 Fractional Multiply/Divide Operations

Up to three PWM pairs with independent timing

Dead time for rising and falling edges

7.14 ns PWM resolution

PWM support for Inverters, PFC, Lighting- BLDC, PMSM, ACIM, SRM

Programmable Fault inputs

Flexible trigger configurations for ADC conversions

ADC module: Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H

Up to three Op amp/Comparators

Op Amp direct connection to the ADC module

Additional dedicated comparator

Programmable references with 32 voltage points for comparators

Charge Time Measurement Unit (CTMU)

12 general purpose timers

Five 16-bit and up to two 32-bit timers/counters

Four OC modules configurable as timers/counters

PTG module with two configurable timers/counters

32-bit Quadrature Encoder Interface (QEI) module configurable as a timer/counter

Four IC modules

Peripheral Trigger Generator (PTG) for scheduling complex sequences

Two UART modules (15 Mbps)

Two 4-wire SPI modules (15 Mbps)

Two I2C™ modules (up to 1 Mbaud) with SMBus support

PPS to allow function remap

Programmable Cyclic Redundancy Check (CRC)

4-channel DMA with user-selectable priority arbitration

UART, SPI, ADC, IC, OC, and Timers