3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS

3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS

Modified Harvard architecture

C compiler optimized instruction set

16-bit wide data path

24-bit wide instructions

16 x 16 multiply operations

32/16 and 16/16 divide operations

USB 2.0 OTG-Compliant Full-Speed Interface

Two CAN™ modules (1 Mbaud)

Four UART modules (15 Mbps) supports LIN/J2602 protocols and IrDA

Four 4-Wire SPI modules (15 Mbps)

Two I2C modules (up to 1 Mbaud) with SMBus Support

Data Converter Interface (DCI) module with Support for I2S and Audio Codecs

PPS to allow Function Remap

Parallel Master Port (PMP)

Programmable Cyclic Redundancy Check (CRC)

Two independent ADC module

One ADC Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H

Second 10-bit ADC has 1.1 Msps with four S&H

Eight S&H using both ADC 10-bit modules

24 analog channels (64-pin devices) up to 32 analog channels (100/121/144-pin devices)

Flexible and independent ADC trigger sources

Up to three Analog Comparator modules

Programmable references with 32 voltage points for Comparators

Nine16-bit Timers/Counters.

16 Input Capture

16 Output Compare/ PWM

Unused Output compares can be used as standard times for a total of 25 timers

Hardware Real-Time Clock and Calendar

Peripheral Pin Select (PPS) to allow function remap

15-channel DMA with user-selectable priority arbitration

UART, USB, SPI, ADC, CAN, IC, OC, Timers, DCI/I2S, PMP