The TPS51362RVER is a high-voltage input, synchronous converter with integrated FET, based on DCAP-2 control topology, which enables fast transient response and supports both POSCAP and all MLCC output capacitors. TI proprietary FET technology combined with TI leading-edge package technology provides the highest density solution for single-output power rail such as VCCIO and VDDQ for DDR notebook memory, or any point-of-load (POL) in wide application.
The key feature of the TPS51362RVER is its ULQ? Mode to enable low-bias current (100 μA in low power mode, enabled by LP#). This feature is extremely beneficial for long battery life in system standby mode.
The feature set includes switching frequency of 800 kHz. Programmable soft-start time with an external capacitor. auto skip, pre-bias startup, integrated bootstrap switch, power good, enable and a full suite of fault protection schemes, including OCL, UVP, OVP, 5-V UVLO and thermal shutdown.
It is packaged in 3.5 mm × 4.5 mm, 0.4-mm pitch, 28-pin QFN (RVE), and specified from –10°C to 85°C.
Feature
Input Voltage Range: 3 V to 22 V
Output Voltage Range: 0.6 V to 2 V
10-A Integrated FET Converter
Fewest External Components
ULQ?-100 Mode of Operation to Enable Long Battery Life During System Standby
Soft-Start Time Programmable by External Capacitor
Switching Frequency: 800 kHz
D-CAP2? Architecture to Enable POSCAP and All MLCC Output Capacitor Usage
Integrated and Temperature Compensated Low-Side On-Resistance Sensing for Accurate OCL Protection
Powergood Output OCL, OVP, UVP and UVLO Protections
Thermal Shutdown (non-latch)
Output Discharge Function
Integrated Boost MOSFET Switch
28-Pin, 3.5-mm × 4.5-mm, RVE, QFN Package with 0.4-mm Pitch and 1-mm Height
Description
The TPS51362 is a high-voltage input, synchronous converter with integrated FET, based on DCAP-2 control topology, which enables fast transient response and supports both POSCAP and all MLCC output capacitors. TI proprietary FET technology combined with TI leading-edge package technology provides the highest density solution for single-output power rail such as VCCIO and VDDQ for DDR notebook memory, or any point-of-load (POL) in wide application.
The key feature of the TPS51362 is its ULQ? Mode to enable low-bias current (100 μA in low power mode, enabled by LP#). This feature is extremely beneficial for long battery life in system standby mode.
The feature set includes switching frequency of 800 kHz. Programmable soft-start time with an external capacitor. auto skip, pre-bias startup, integrated bootstrap switch, power good, enable and a full suite of fault protection schemes, including OCL, UVP, OVP, 5-V UVLO and thermal shutdown.
It is packaged in 3.5 mm × 4.5 mm, 0.4-mm pitch, 28-pin QFN (RVE), and specified from –10°C to 85°C.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
