DDR Memory Termination Regulators, Texas Instruments
Designed specifically for bus termination in DDR and QDR memory applications. These sink/source tracking termination regulators are aimed for space saving, low-cost applications with low external part counts.
Feature
Independent Dual-Outputs Operate 180° Out of Phase
Wide Input Voltage Range: 4.5-V – 28-V
Adjustable Output Voltage Down to 0.9 V
Pin-Selectable PWM/SKIP Mode for High Efficiency Under Light Loads
Synchronous Buck Operation Allows up to 95% Efficiency
Separate Standby Control and Overcurrent Protection for Each Channel
Programmable Short-Circuit Protection
Low Supply (1 mA) and Shutdown (1 nA) Current
Power Good Output
High-Speed Error Amplifiers
Sequencing Easily Achieved by Selecting Softstart Capacitor Values.
5-V Linear Regulator Power Internal IC Circuitry
30-Pin TSSOP Packaging
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
