The MachXO2 family of ultra-low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.
Feature
Flexible logic architecture
Ultra low power devices
Embedded and distributed memory
On-chip user flash memory
Pre-engineered source synchronous I/O
High performance, flexible I/O buffer
Flexible on-chip clocking
Non-volatile, infinitely reconfigurable
TransFR™ Reconfiguration
Enhanced system level support
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
