The TPS54162 is a step-down switch-mode power supply with a voltage supervisor and an integrated NMOS switching FET. Integrated input voltage line feed forward topology improves line transient regulation of the voltage mode buck regulator. The regulator has a cycle-by-cycle current limit. The device also features low-power mode operation under light load conditons which reduces the supply current to 50 μA (typical). By pulling the EN pin low, the supply shutdown current is reduced to 1 μA (typical).
An open drain reset signal indicates when the nominal output drops below the reset threshold set by an external resistor divider network. The output voltage start up ramp is controlled by a soft start capacitor. There is an internal undervoltage shut down which is activated when the input supply ramps down to 2.6 V. The device is protected during an overload condition on output by frequency fold back operation, and also has a thermal shutdown protection.
Feature
Asynchronous Switch Mode Regulator
3.6 V to 48 V Operating Range, Withstands Transients up to 60 V
1 A Maximum Load Current
50 μA Typical Quiescent Current
200 kHz to 2.2 MHz Switching Frequency
0.8 V ± 1.5% Voltage Reference
High Voltage Tolerant Enable Input
Soft Start on Enable Cycle
Slew Rate Control on Internal Power Switch
Low-Power Mode for Light Load Conditions
Programmable Delay for Power-On Reset
External Compensation for Error Amplifier
Reset Function Filter Time for Fast Negative Transients
Programmable Overvoltage, Undervoltage Output Monitor
Thermal Sensing and Shutdown
Switch Current Limit Protection
Short Circuit and Overcurrent Protection of FET
Junction Temperature Range: –40°C to 150°C
20-Pin HTSSOP PowerPAD? Package
APPLICATIONS
Description
The TPS54162 is a step-down switch-mode power supply with a voltage supervisor and an integrated NMOS switching FET. Integrated input voltage line feed forward topology improves line transient regulation of the voltage mode buck regulator. The regulator has a cycle-by-cycle current limit. The device also features low-power mode operation under light load conditons which reduces the supply current to 50 μA (typical). By pulling the EN pin low, the supply shutdown current is reduced to 1 μA (typical).
An open drain reset signal indicates when the nominal output drops below the reset threshold set by an external resistor divider network. The output voltage start up ramp is controlled by a soft start capacitor. There is an internal undervoltage shut down which is activated when the input supply ramps down to 2.6 V. The device is protected during an overload condition on output by frequency fold back operation, and also has a thermal shutdown protection.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
