These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
The -1 version of the SN74ALS245ADBR is identical to the standard version, except that the recommended maximum IOL is increased to 48 mA. There is no -1 version of the SN54ALS245A.
Feature
4.5-V to 5.5-V VCC Operation
Max tpd of 5.5 ns at 5 V
3-State Outputs Drive Bus Lines Directly
pnp Inputs Reduce dc Loading
Description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOL is increased to 48 mA. There is no -1 version of the SN54ALS245A.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
