The 74LVC1G08GW is a single two input AND gate in 5 pin TSSOP package. Inputs can be driven either from 3.3V or 5V devices. This feature allows the use of this device as translators in mixed 3.3V and 5V applications. Schmitt trigger action at all input makes circuit tolerant of slower input rise and fall time. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output and prevents damaging due to backflow current through the device during powered down mode.
Feature
Wide supply voltage range from 1.65V to 5.5V
High noise immunity
Complies with JESD8-7, JESD8-5, JESD8-B/JESD36 JEDEC standards
±24mA output drive at VCC = 3V
CMOS low power consumption
Latch up performance is less than or equal to 250mA
Direct interface with TTL levels
Input voltages up to 5V
Features ESD protection
Ambient temperature range from -40°C to 125°C
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
