The MAX809STRG is a Supervisor Circuit with active-low RESET output. The 3-pin microprocessor reset monitor designed to monitor VCC in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within 10 seconds of VCC falling through the reset voltage threshold. Reset is maintained active for a timeout period which is trimmed by the factory after VCC rises above the reset threshold. It is optimized to reject fast transient glitches on the VCC line.
Feature
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
