The Smart Reset? devices provide a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset? input delay time (tSRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push-buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time tSRCcauses a hard reset of the processor through the reset output.
The STM6524AUABDL6F has two combined delayed Smart Reset? inputs (SR0,SR1) with preset delayed Smart Reset? setup time (tSRC). The reset output is asserted after both of the Smart Reset? inputs were held active for the selected tSRCdelay time. Depending on selected option theRSToutput remains asserted either until at least oneSRinput goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC(i.e. factory-programmed). The reset output,RST, is active low or active high, push-pull or open drain with optional pull-up resistor. The device fully operates over a broad VCCrange 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.

Feature