MAX V device CPLD, Altera
Low-power, and non-volatile CPLD architecture
Instant-on (0.5ms or less) configuration time
Standby current as low as 25μA and fast power-down/reset operation
Fast propagation delay and clock-to-output times
Internal oscillator
Feature
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
