Maxim's redesigned DG411/DG412/DG413CJ+ analog switches now feature low on-resistance matching between switches (3Ω max) and guaranteed on-resistance flatness over the signal range (Δ4Ω max). These low on-resistance switches conduct equally well in either direction. They guarantee low charge injection, low power consumption, and an ESD tolerance of 2000V minimum per Method 3015.7. The new design offers lower off-leakage current over temperature (less than 5nA at +85°C). The DG411/DG412/DG413CJ+ are quad, single-pole/single-throw (SPST) analog switches. The DG411 is normally closed (NC), and the DG412 is normally open (NO). The DG413CJ+ has two NC switches and two NO switches. Switching times are less than 150ns max for tON and less than 100ns max for tOFF. These devices operate from a single +10V to +30V supply, or bipolar ±4.5V to ±20V supplies. Maxim's improved DG411/DG412/DG413CJ+ are fabricated with a 44V silicon-gate process.
Feature
Plug-In Upgrade for Industry-Standard DG411/DG412/DG413
Improved RDS(ON) Match Between Channels (3Ω max)
Guaranteed RFLAT(ON) Over Signal Range (Δ4Ω)
Improved Charge Injection (10pC max)
Improved Off-Leakage Current Over Temperature(< 5nA at +85°C)
Withstand Electrostatic Discharge (2000V min) per Method 3015.7
Existing Features
Low RDS(ON)(35Ω max)
Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20V
Low Power Consumption (35μW max)
Rail-to-Rail Signal Handling
TTL/CMOS-Logic Compatible
Applications
Audio Signal Routing
Battery-Operated Systems
Communication Systems
Heads-Up Displays
Military Radios
PBX, PABX
Sample-and-Hold Circuits
Test Equipment
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
